WEBVTT

00:12.360 --> 00:16.200
Rehab a test bench for the universal shift register.

00:16.330 --> 00:20.790
And so I'm just going to kind of quickly run through and just show you different parts of the test bench

00:20.860 --> 00:25.180
and you can kind of see what's going on to give you an idea of what to expect when you're creating a

00:25.180 --> 00:26.100
test bench.

00:26.320 --> 00:32.950
So the first line we have a library instantiation where we call in show libraries which we're now I'm

00:32.950 --> 00:35.380
sure you're somewhat familiar with.

00:35.380 --> 00:42.940
And we also have the libraries that are only use in the test bench on line 6 and 7 9 9.

00:42.960 --> 00:49.210
We're calling it a custom package that when you get to the lab section and you have to start creating

00:49.210 --> 00:55.210
and test benches I give you the files you need and show you how to them how to structure your folder

00:55.210 --> 00:59.790
so that you can use the sim them in that package.

01:00.120 --> 01:08.080
And we have the entity declaration which is called test us are then our component USAR which is the

01:08.950 --> 01:09.820
beach of design.

01:09.820 --> 01:13.960
We want to test and we go ahead and define the signals and constants.

01:13.960 --> 01:20.290
We're going to use to actually test universal shift register and then right or anything begin we have

01:20.290 --> 01:26.860
our device running tests which is us our go ahead and use a generic map port map to go ahead and generate

01:26.860 --> 01:31.540
this universal shift register and then we have our stimulus process.

01:31.900 --> 01:36.530
And in our stimulus process we have several different variables in that line right.

01:36.850 --> 01:45.760
And what these do are they're going to read in values from a text file or from a text file we're using

01:46.290 --> 01:54.340
and that will go ahead and essentially we're going to take these ideas from that infamous text file

01:54.400 --> 01:56.820
and it's going to compare him to the baddies.

01:56.830 --> 02:03.040
We actually get from the actual universal shift register and make sure the inputs match the outputs.

02:03.230 --> 02:06.050
And so that's essentially exactly what's going on here.

02:06.160 --> 02:13.480
We are reading in these by an input line in char and we're converting them to ask you to hack's which

02:13.480 --> 02:17.810
is what the function is declared and send them.

02:17.920 --> 02:22.600
And it all package and then we're going to read the line output line.

02:22.600 --> 02:29.260
We have a clock that we're toggling in 0 and 1 and then we have this wait for 10 seconds which is allows

02:29.290 --> 02:37.440
us to wait and toggle our clock back and forth and then we do have at the very end we kind of have a

02:38.130 --> 02:45.460
this this error reporting where if it's successful or if there's no we don't count any errors then we

02:45.460 --> 02:49.660
know it's a success and we can say success us our task completed.

02:49.900 --> 02:55.540
However otherwise we know that our device is broken or you can write whatever whatever type of warning

02:55.540 --> 02:59.010
you would like to use.

02:59.240 --> 03:03.550
Now I was just kind of a quick overview of what the U.S. Our testbench is like.