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Here's a walkthrough of just kind of example outline of what a test bench would look like.

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Now this actual This code here wouldn't actually work.

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It's just kind of a skeleton or like what a test bench would look like.

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So if you look at line 1 we've got comments and then lines three through five are where we call in the

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libraries as well as standard logic 1 1 6 4.

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Also the numeric standard model all which allows us to use the center vector center logic vectors and

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the signed and unsigned types.

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Now libraries that are only supporter in test benches you can see here we have as the standard text

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I know and standard logic text.

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And this allows us to actually read in values from a text file.

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We have the entity which we just whatever name we call the testbench which normally we call it test

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underscore whatever the name of the actual design you're testing.

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And then we have the architecture test and this is where we instantiate the component of the VHDL entity

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we're testing.

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And we have the component names we essentially do the component instantiation and then in the to do

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section right on line 25 we want to create signals that we're going to use in our testbench.

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And then after that in the begin we want to call some of them to test but we'll create the name of entity

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to.

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We're testing port map and everything there.

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And then we'll have our expected process.

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Mine 33 and this is just a process where we're going to specify.

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It's going to give us the results we want.

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So the testbench is essentially we're generating inputs and this is a stimulus process 140 or C that

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is where we're actually generating inputs to put on the shelf while we are we're testing and then we

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want to check the outputs unexpected process and the end if we get if the results are not what we expect

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then we know that our design is not working correctly.

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And so that's just kind of how novio But what a test bench looks like and kind of what when we create

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one this is kind of what the code will look like.