WEBVTT 00:12.310 --> 00:18.340 Welcome to the test bench introduction lecture and this lecture I'm going to introduce and explain what 00:18.330 --> 00:21.290 a test benches and how that can be used. 00:22.070 --> 00:30.130 A test bench is a model that is used to exercise and verify that your VHDL design is working as you'd 00:30.130 --> 00:31.050 expect. 00:31.310 --> 00:36.300 This is where when you're using these test benches is where most of your debugging will occur. 00:36.320 --> 00:42.800 They're used to verify that the timing and logically that your design is doing as you'd expect when 00:42.800 --> 00:44.830 you're working with me it's G.L.. 00:44.840 --> 00:50.930 The challenge is unlike software development you can't emulate or pause your design right in the middle 00:50.930 --> 00:54.080 as it's running and read the value of variables. 00:54.080 --> 00:56.380 You don't have that actual capability. 00:56.390 --> 01:01.010 So with a testbench you can simulate and see what your variables are doing. 01:01.010 --> 01:06.470 And so you can then make the changes accordingly when you're working with a testbench it is most ideal 01:06.470 --> 01:13.370 to have a separate party develop the testbench if at all possible you like for example you want to be 01:13.670 --> 01:16.630 creating the design you want someone else to create the testbench. 01:16.790 --> 01:19.980 That way the testbench has an air or reports in air. 01:20.210 --> 01:27.010 You can then determine either a design is being implemented wrong or B testbench is wrong. 01:27.050 --> 01:32.600 For example if I create a test testbench and I create the design I may create the design wrong and if 01:32.600 --> 01:38.060 I create the test bench wrong making or that's how the design should operate then the test bench is 01:38.120 --> 01:39.500 not of any help to me. 01:40.260 --> 01:46.650 With test benches they consist of an entity and an architecture that entity is empty. 01:46.650 --> 01:48.570 There is no ports or generics. 01:48.570 --> 01:55.140 The architecture it declares that instantiates the design that you want to test and then also the architecture 01:55.360 --> 02:00.450 we're in and generates stimulus that we're in apply to the design we want to test and we'll verify the 02:00.450 --> 02:03.670 response and see what the outputs are. 02:03.750 --> 02:10.590 So just looking at a diagram of what testbench is doing we have our entity to be tested or in this case 02:10.590 --> 02:12.720 the Beechfield design that we create. 02:12.990 --> 02:19.860 And we're going to apply stimulus or simulate in Gennari I want these inputs such as push buttons switches 02:20.190 --> 02:25.590 or other type of inputs you have to your system or design and then you're going to verify the outputs 02:25.650 --> 02:31.740 and see what they are and check if they're correct or also view them on a waveform window to kind of 02:31.740 --> 02:36.510 see how they relate to each other and make sure design is operating as as you expect. 02:37.830 --> 02:43.950 Now when you're working with these test benches these are testing only you cannot synthesize them and 02:43.950 --> 02:45.650 put them on a FPGA. 02:45.650 --> 02:47.730 They are not synthesize they'll give you errors. 02:47.790 --> 02:49.620 There's no actual running designs. 02:49.740 --> 02:58.110 They're simply used only for testing and a test bench can reference from or put in values from outside 02:58.110 --> 02:59.890 files such as text files. 02:59.970 --> 03:06.030 You can use these text files to say create different hex codes you want to apply as an input to your 03:06.030 --> 03:10.560 design and so you can reference these and put them in there but you just have to realize that when you're 03:10.620 --> 03:16.770 writing a testbench for synthesizer will code they are two different and their architectures are different 03:16.770 --> 03:23.100 and they look different and you can actually put a testbench code on the FPGA they're simply for testing 03:23.100 --> 03:27.380 only when you're developing these test benches. 03:27.380 --> 03:35.280 You can code this completely from scratch using any VHDL editor or tool or notepad notepad plus plus 03:36.020 --> 03:43.760 if you're working with Xilinx ISC Xining Silverado or Altera you can get a testbench skeleton to work 03:43.770 --> 03:44.180 from. 03:44.240 --> 03:49.260 So if you click in any one of these three tools you can say I want a testbench file. 03:49.280 --> 03:55.340 It will give you a skeleton so it'll give you the entity and instantiate that device but then you still 03:55.340 --> 04:01.530 have to tell it or generate the stimulus for this testbench. 04:01.560 --> 04:02.970 Now you know in test benches. 04:02.970 --> 04:05.670 Let's take a look at the structure of a VHDL testbench.