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Welcome to the test bench introduction lecture and this lecture I'm going to introduce and explain what

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a test benches and how that can be used.

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A test bench is a model that is used to exercise and verify that your VHDL design is working as you'd

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expect.

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This is where when you're using these test benches is where most of your debugging will occur.

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They're used to verify that the timing and logically that your design is doing as you'd expect when

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you're working with me it's G.L..

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The challenge is unlike software development you can't emulate or pause your design right in the middle

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as it's running and read the value of variables.

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You don't have that actual capability.

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So with a testbench you can simulate and see what your variables are doing.

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And so you can then make the changes accordingly when you're working with a testbench it is most ideal

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to have a separate party develop the testbench if at all possible you like for example you want to be

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creating the design you want someone else to create the testbench.

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That way the testbench has an air or reports in air.

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You can then determine either a design is being implemented wrong or B testbench is wrong.

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For example if I create a test testbench and I create the design I may create the design wrong and if

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I create the test bench wrong making or that's how the design should operate then the test bench is

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not of any help to me.

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With test benches they consist of an entity and an architecture that entity is empty.

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There is no ports or generics.

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The architecture it declares that instantiates the design that you want to test and then also the architecture

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we're in and generates stimulus that we're in apply to the design we want to test and we'll verify the

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response and see what the outputs are.

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So just looking at a diagram of what testbench is doing we have our entity to be tested or in this case

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the Beechfield design that we create.

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And we're going to apply stimulus or simulate in Gennari I want these inputs such as push buttons switches

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or other type of inputs you have to your system or design and then you're going to verify the outputs

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and see what they are and check if they're correct or also view them on a waveform window to kind of

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see how they relate to each other and make sure design is operating as as you expect.

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Now when you're working with these test benches these are testing only you cannot synthesize them and

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put them on a FPGA.

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They are not synthesize they'll give you errors.

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There's no actual running designs.

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They're simply used only for testing and a test bench can reference from or put in values from outside

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files such as text files.

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You can use these text files to say create different hex codes you want to apply as an input to your

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design and so you can reference these and put them in there but you just have to realize that when you're

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writing a testbench for synthesizer will code they are two different and their architectures are different

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and they look different and you can actually put a testbench code on the FPGA they're simply for testing

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only when you're developing these test benches.

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You can code this completely from scratch using any VHDL editor or tool or notepad notepad plus plus

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if you're working with Xilinx ISC Xining Silverado or Altera you can get a testbench skeleton to work

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from.

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So if you click in any one of these three tools you can say I want a testbench file.

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It will give you a skeleton so it'll give you the entity and instantiate that device but then you still

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have to tell it or generate the stimulus for this testbench.

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Now you know in test benches.

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Let's take a look at the structure of a VHDL testbench.