VHDL Modeling Concepts

Basic VHDL concepts for behavioral and structural modeling

As an example, we look at ways of describing a four-bit register, shown in

Figure 2-1.

Using VHDL terminology, we call the module reg4 a design entity, and the inputs

and outputs are ports. Figure 2-2 shows a VHDL description of the interface to this

entity. This is an example of an entity declaration. It introduces a name for the entity

and lists the input and output ports, specifying that they carry bit values (‘0’ or ‘1’) into

and out of the entity. From this we see that an entity declaration describes the external view of the entity.