WEBVTT

00:12.900 --> 00:22.390
With the full hour here we have an example of a four hour in a data flow sort of type of structure or

00:22.400 --> 00:25.770
architecture and just looking at it on the right.

00:25.790 --> 00:33.380
We've got the digital logic circuit of a full outer or three and puts x y and s.i and then we have our

00:33.380 --> 00:37.080
outputs s and CEO or carry out.

00:37.550 --> 00:47.180
And if you look on the left on in our viewer DL file on lines 5 is where we have our entity declaration

00:47.570 --> 00:57.620
where we're declaring that the are is for one which is describing what our actual circuit is and then

00:57.620 --> 01:00.190
we have the port which is orbit of finding the inputs and outputs.

01:00.200 --> 01:06.230
And you can see that we have assets and see out of the outputs which if you look at the digital circuit

01:06.350 --> 01:13.150
that is the same as an SEO which is calling us you know I mean for inputs X Y and C.

01:13.320 --> 01:17.190
And so just looking at you you can see that that's kind of how it correlates.

01:17.240 --> 01:25.670
Now the architecture on line 14 is where we're actually describing what is going on.

01:25.680 --> 01:31.580
And so if you look you'll see in the architecture we have 1 2 and gates.

01:31.580 --> 01:35.800
If you look at the digital logic circuit you see we have two and Gates as well.

01:36.260 --> 01:44.570
And also if you look in architecture where you've got two three exclusive OR gates that take the back

01:44.570 --> 01:47.750
side we have two three exclusive OR gates.

01:47.750 --> 01:52.970
And if you look just between the digital logic circuit on the right on the beach you know you can see

01:52.970 --> 01:54.690
that the two correlate.

01:54.710 --> 02:02.800
So looking at the sea out it is equal to see in ANDed with X exclusive board with Y.

02:02.840 --> 02:12.620
If you look and see if we have X and Y there being exclusive award and then we or that value with X

02:12.740 --> 02:21.030
and Y and so just just following the actual architecture of the four outer one we can see that it's

02:21.050 --> 02:27.050
doing exactly what we're describing exactly how we want the gauge to place how many gates we want and

02:27.050 --> 02:28.570
where we want them to placed.

02:28.640 --> 02:30.940
And so that's kind of idea when you're working with the data flow.

02:30.950 --> 02:33.890
That's essentially what you're doing in here.

02:34.040 --> 02:41.560
More important though just want to show you that if you look on the VHDL file we have our poor where

02:41.560 --> 02:51.590
we define or put X Y and C in our outputs S and C out and this is all an entity section of the four

02:51.610 --> 02:52.370
outer.

02:52.560 --> 02:56.870
And if you look in the architecture section this is where we're defining what's actually going on.

02:56.870 --> 03:02.780
So the architecture section is the actual gates and the signals between the gates connecting everything

03:03.170 --> 03:03.950
together.

03:04.100 --> 03:06.810
And that is defined in the architecture section.

03:06.830 --> 03:14.360
After we have the begin keyword we define what are see out in what Guess how these outputs are defined

03:14.360 --> 03:18.410
based upon the inputs where you have declared and the statements.