WEBVTT 00:12.760 --> 00:19.460 Welcome to the VHDL design architecture styles lecture in this lecture I'm going to talk to you about 00:19.550 --> 00:26.130 the different styles you can use when you design the architecture of your VHDL design. 00:26.450 --> 00:33.980 So VHDL designs all have to have an entity in architecture in a way design the architecture is you can 00:33.980 --> 00:42.200 use various different ways and three of the common ways are structural behavioral and dataflow structural 00:42.260 --> 00:49.840 design uses component instantiations where we have pre completed HGL designs that we're going to stanchly 00:49.850 --> 00:52.400 in use in our design. 00:52.400 --> 00:59.560 You also have behavioral style which is process statements and we specify the behavior. 00:59.570 --> 01:01.320 Hence the name behavioral. 01:01.350 --> 01:05.830 The behavior of the architecture and we just tell it how we want it to work. 01:05.990 --> 01:12.450 And the compiler determines the number of gates and everything else to make it operate in that way. 01:12.500 --> 01:19.190 And a dataflow style is where we use boolean logic and concurrent signal assignments to the data flow 01:19.200 --> 01:26.180 style we're specifically telling the signals that are coming in which and gates where the OR gates are 01:26.450 --> 01:30.590 and all the different logical gates that are going on of our design. 01:31.130 --> 01:37.100 So we're going to go ahead and walk through all of the different different styles and what we're going 01:37.100 --> 01:44.450 to do is we have a full adder that we're going to go through a behavioral and data flow and the structural 01:44.450 --> 01:49.670 design examples where we're designing the same exact thing we're designing a ladder. 01:49.760 --> 01:54.150 We're just going to use three different architecture styles to do that. 01:54.330 --> 02:01.010 So real quick I'm just going to show you what explain why Flattr is a FULL OUTER has three inputs. 02:01.160 --> 02:04.590 We've got an x y and a Carian. 02:04.660 --> 02:08.200 And you have two outputs carry out and your some. 02:08.210 --> 02:09.920 So what's going on. 02:09.920 --> 02:16.130 We have a truth table but you've got three different inputs and there's no way to assign to these inputs 02:16.130 --> 02:19.880 so the maxim that you could have is a total value of three. 02:19.940 --> 02:24.260 And so it takes whatever the inputs are and gives you the sum on the output. 02:24.260 --> 02:31.550 So if I put my X Y or c in any of those are one and the rest are zeros my output is going to be a 1 02:31.550 --> 02:32.360 on the sum. 02:32.510 --> 02:39.340 And if I put all three are in then I'll have a two on the output and binary gives me a value 3. 02:39.390 --> 02:44.690 So real we're doing is taking Addai as x y and C and and adding them. 02:44.720 --> 02:48.980 So the first example we have let's just talk about a behavioral style architecture. 02:49.130 --> 02:55.220 So a behavioral style architecture does not imply a specific harbor implementation. 02:55.220 --> 03:00.020 We leave this hardware implementation up to the synthesizer that we're using. 03:00.140 --> 03:07.490 And so we simply tell a circuit how we want to behave and the synthesizer will based upon we tell it's 03:07.490 --> 03:12.460 specific timing requirements and it will say OK I think you know it's best served to have an endgame 03:12.490 --> 03:20.840 here and or gate there or whatever it deems the fastest or to meet your requirements by using a behavior 03:20.840 --> 03:21.800 style. 03:21.830 --> 03:27.630 It allows the compiler to determine exactly the the specific implementation. 03:27.890 --> 03:34.500 And I believe behavioral styles are one of the easiest ways to read if you have a fairly complex design. 03:34.550 --> 03:38.030 It is sometimes can be a lot more easy to read. 03:38.030 --> 03:44.480 So let's take an example of the Flader have we're going to use the behavioral data style. 03:44.480 --> 03:49.430 So I'm not going to go through line by line exactly the entire code but it does kind of give you a rough 03:49.460 --> 03:54.770 overview of what's going on and you can kind of see the styles because really important thing here is 03:55.070 --> 03:57.060 to understand the different styles. 03:57.230 --> 04:02.990 So at the beginning we have you know our library we instantiate all of our library using we have the 04:02.990 --> 04:09.890 entity that's telling us our inputs and outputs Terfel that are we have our X Y and C in our ass and 04:09.890 --> 04:12.140 our C out as their outputs. 04:12.140 --> 04:15.530 And then we have the architecture and this is what we're focused on. 04:15.590 --> 04:22.400 So we have the architecture we're calling it behavior and we have our signals inputs and our signal 04:22.430 --> 04:30.770 outputs where we have our signal assignments where we're assigning or inputs the values of c and x Y 04:31.450 --> 04:37.610 and R C out as our outputs one ass as our outputs zero. 04:37.610 --> 04:40.220 Now the key here with the behavioral example. 04:40.250 --> 04:47.510 The big thing we're doing is we have a process we're calling at her proc and in this process we're giving 04:47.510 --> 04:54.980 it a case statement where we're saying our inputs given we have three inputs and for every single case 04:55.370 --> 04:57.260 we're telling you what the outputs should be. 04:57.260 --> 05:02.750 So we're doing a behavior we're saying hey here's our design this how we want it to behave. 05:02.750 --> 05:07.490 Now you go ahead and implement the gates or gates and everything needed to implement this Flader. 05:07.520 --> 05:16.340 But I know that given these inputs I want these outputs and this behavioral style of a flatter the data 05:16.390 --> 05:18.030 flow architecture. 05:18.440 --> 05:24.410 This is what we tell the compiler how to implement the VHDL file by specifically telling it we want 05:24.410 --> 05:30.350 an AND gate here or gate there and you can think of this like we are specifically telling you how we 05:30.350 --> 05:33.130 want the data to flow through our design. 05:33.290 --> 05:35.930 Hence the name dataflow architecture. 05:36.940 --> 05:42.460 So let's take a look at example we have we're going to implement the FLATTR again but this time instead 05:42.460 --> 05:46.830 of a behavioral style We're going to use a dataflow architecture. 05:46.960 --> 05:48.420 So we have the entity. 05:48.460 --> 05:50.990 The libraries are the exact same. 05:51.010 --> 05:54.610 However we have the architecture is the only difference. 05:54.670 --> 06:04.600 So if you'll notice we have after our begin or see out is equal to r c and value added with our X input 06:04.690 --> 06:13.360 exclusive or with our Y input and the result of that is logically ored with the result of the X and 06:13.480 --> 06:23.260 logical ended with the Y input and are some r s value is equal to our X exclusively or with R Y which 06:23.260 --> 06:25.980 is exclusively or with R C in. 06:26.080 --> 06:30.510 And so this is doing the same exact thing as a behavioral style. 06:30.520 --> 06:35.650 This is going to result in the same exact circuitry except in our data flow we're telling exactly which 06:35.650 --> 06:42.340 dates to use that are behavioral synthesizer is determining the gates we're using with a structural 06:42.340 --> 06:43.320 architecture. 06:43.480 --> 06:48.490 This is where you will contain component instantiations of previous designs you've worked on. 06:48.490 --> 06:53.770 This is typically if you have a more complex design or a system where you have a lot of stuff going 06:53.770 --> 06:57.130 on you may have a B and C already completed. 06:57.220 --> 07:01.930 So you pull those designs in and add some of your own custom logic and kind of internally wire them 07:01.930 --> 07:02.830 together. 07:03.160 --> 07:06.740 And we also may include a little bit dataflow style in here. 07:06.970 --> 07:12.660 This is when you're working with complex designs or a lot of times is a very common way of doing things. 07:13.920 --> 07:16.000 So let's take a look at a structural example. 07:16.050 --> 07:25.280 So at a top level we're still doing a full adder and a full outer is created by as is 2 1/2 adder's 07:25.560 --> 07:31.350 So we have a half adder makes the whole design file which you can see we have the half after half an 07:31.340 --> 07:33.380 hour and an OR gate. 07:33.480 --> 07:41.100 And with these 2 1/2 hours in or DAY we're going to create a structural design or FLATTR so with our 07:41.100 --> 07:49.350 structural example we have the library and entity which is the same exact as our data flow and our behavioral 07:49.350 --> 07:50.280 styles. 07:50.280 --> 07:57.120 Now the structural style we have this component instantiation we're instantiating a half after which 07:57.120 --> 08:07.290 contains a Kerry s a and b and we have our internal signals which are half some carry and carry two. 08:07.500 --> 08:11.220 And then what we're doing is we're in stanching or half at or twice. 08:11.250 --> 08:19.140 So we have half hour one and half hour or two and we're assigning these values carry one half some x 08:19.320 --> 08:27.510 y carry to X half some and C in and if you'll notice you look at the carry one and carry two and half 08:27.510 --> 08:34.470 some and how they correlate with the top view block diagram and then we also have a or gate where we're 08:34.470 --> 08:37.070 offering our carry one with our carry two. 08:37.090 --> 08:39.660 And so this is how you implement structural design. 08:39.650 --> 08:46.100 We have this half hour design which is located off somewhere else a separate Be it showed as I M-file. 08:46.230 --> 08:49.120 And we're doing a good point instantiation and it together. 08:50.450 --> 08:53.420 Now you've covered all the different aspects of the design. 08:53.420 --> 08:55.200 Let's start looking at some examples.