1 00:00:12,760 --> 00:00:19,460 Welcome to the VHDL design architecture styles lecture in this lecture I'm going to talk to you about 2 00:00:19,550 --> 00:00:26,130 the different styles you can use when you design the architecture of your VHDL design. 3 00:00:26,450 --> 00:00:33,980 So VHDL designs all have to have an entity in architecture in a way design the architecture is you can 4 00:00:33,980 --> 00:00:42,200 use various different ways and three of the common ways are structural behavioral and dataflow structural 5 00:00:42,260 --> 00:00:49,840 design uses component instantiations where we have pre completed HGL designs that we're going to stanchly 6 00:00:49,850 --> 00:00:52,400 in use in our design. 7 00:00:52,400 --> 00:00:59,560 You also have behavioral style which is process statements and we specify the behavior. 8 00:00:59,570 --> 00:01:01,320 Hence the name behavioral. 9 00:01:01,350 --> 00:01:05,830 The behavior of the architecture and we just tell it how we want it to work. 10 00:01:05,990 --> 00:01:12,450 And the compiler determines the number of gates and everything else to make it operate in that way. 11 00:01:12,500 --> 00:01:19,190 And a dataflow style is where we use boolean logic and concurrent signal assignments to the data flow 12 00:01:19,200 --> 00:01:26,180 style we're specifically telling the signals that are coming in which and gates where the OR gates are 13 00:01:26,450 --> 00:01:30,590 and all the different logical gates that are going on of our design. 14 00:01:31,130 --> 00:01:37,100 So we're going to go ahead and walk through all of the different different styles and what we're going 15 00:01:37,100 --> 00:01:44,450 to do is we have a full adder that we're going to go through a behavioral and data flow and the structural 16 00:01:44,450 --> 00:01:49,670 design examples where we're designing the same exact thing we're designing a ladder. 17 00:01:49,760 --> 00:01:54,150 We're just going to use three different architecture styles to do that. 18 00:01:54,330 --> 00:02:01,010 So real quick I'm just going to show you what explain why Flattr is a FULL OUTER has three inputs. 19 00:02:01,160 --> 00:02:04,590 We've got an x y and a Carian. 20 00:02:04,660 --> 00:02:08,200 And you have two outputs carry out and your some. 21 00:02:08,210 --> 00:02:09,920 So what's going on. 22 00:02:09,920 --> 00:02:16,130 We have a truth table but you've got three different inputs and there's no way to assign to these inputs 23 00:02:16,130 --> 00:02:19,880 so the maxim that you could have is a total value of three. 24 00:02:19,940 --> 00:02:24,260 And so it takes whatever the inputs are and gives you the sum on the output. 25 00:02:24,260 --> 00:02:31,550 So if I put my X Y or c in any of those are one and the rest are zeros my output is going to be a 1 26 00:02:31,550 --> 00:02:32,360 on the sum. 27 00:02:32,510 --> 00:02:39,340 And if I put all three are in then I'll have a two on the output and binary gives me a value 3. 28 00:02:39,390 --> 00:02:44,690 So real we're doing is taking Addai as x y and C and and adding them. 29 00:02:44,720 --> 00:02:48,980 So the first example we have let's just talk about a behavioral style architecture. 30 00:02:49,130 --> 00:02:55,220 So a behavioral style architecture does not imply a specific harbor implementation. 31 00:02:55,220 --> 00:03:00,020 We leave this hardware implementation up to the synthesizer that we're using. 32 00:03:00,140 --> 00:03:07,490 And so we simply tell a circuit how we want to behave and the synthesizer will based upon we tell it's 33 00:03:07,490 --> 00:03:12,460 specific timing requirements and it will say OK I think you know it's best served to have an endgame 34 00:03:12,490 --> 00:03:20,840 here and or gate there or whatever it deems the fastest or to meet your requirements by using a behavior 35 00:03:20,840 --> 00:03:21,800 style. 36 00:03:21,830 --> 00:03:27,630 It allows the compiler to determine exactly the the specific implementation. 37 00:03:27,890 --> 00:03:34,500 And I believe behavioral styles are one of the easiest ways to read if you have a fairly complex design. 38 00:03:34,550 --> 00:03:38,030 It is sometimes can be a lot more easy to read. 39 00:03:38,030 --> 00:03:44,480 So let's take an example of the Flader have we're going to use the behavioral data style. 40 00:03:44,480 --> 00:03:49,430 So I'm not going to go through line by line exactly the entire code but it does kind of give you a rough 41 00:03:49,460 --> 00:03:54,770 overview of what's going on and you can kind of see the styles because really important thing here is 42 00:03:55,070 --> 00:03:57,060 to understand the different styles. 43 00:03:57,230 --> 00:04:02,990 So at the beginning we have you know our library we instantiate all of our library using we have the 44 00:04:02,990 --> 00:04:09,890 entity that's telling us our inputs and outputs Terfel that are we have our X Y and C in our ass and 45 00:04:09,890 --> 00:04:12,140 our C out as their outputs. 46 00:04:12,140 --> 00:04:15,530 And then we have the architecture and this is what we're focused on. 47 00:04:15,590 --> 00:04:22,400 So we have the architecture we're calling it behavior and we have our signals inputs and our signal 48 00:04:22,430 --> 00:04:30,770 outputs where we have our signal assignments where we're assigning or inputs the values of c and x Y 49 00:04:31,450 --> 00:04:37,610 and R C out as our outputs one ass as our outputs zero. 50 00:04:37,610 --> 00:04:40,220 Now the key here with the behavioral example. 51 00:04:40,250 --> 00:04:47,510 The big thing we're doing is we have a process we're calling at her proc and in this process we're giving 52 00:04:47,510 --> 00:04:54,980 it a case statement where we're saying our inputs given we have three inputs and for every single case 53 00:04:55,370 --> 00:04:57,260 we're telling you what the outputs should be. 54 00:04:57,260 --> 00:05:02,750 So we're doing a behavior we're saying hey here's our design this how we want it to behave. 55 00:05:02,750 --> 00:05:07,490 Now you go ahead and implement the gates or gates and everything needed to implement this Flader. 56 00:05:07,520 --> 00:05:16,340 But I know that given these inputs I want these outputs and this behavioral style of a flatter the data 57 00:05:16,390 --> 00:05:18,030 flow architecture. 58 00:05:18,440 --> 00:05:24,410 This is what we tell the compiler how to implement the VHDL file by specifically telling it we want 59 00:05:24,410 --> 00:05:30,350 an AND gate here or gate there and you can think of this like we are specifically telling you how we 60 00:05:30,350 --> 00:05:33,130 want the data to flow through our design. 61 00:05:33,290 --> 00:05:35,930 Hence the name dataflow architecture. 62 00:05:36,940 --> 00:05:42,460 So let's take a look at example we have we're going to implement the FLATTR again but this time instead 63 00:05:42,460 --> 00:05:46,830 of a behavioral style We're going to use a dataflow architecture. 64 00:05:46,960 --> 00:05:48,420 So we have the entity. 65 00:05:48,460 --> 00:05:50,990 The libraries are the exact same. 66 00:05:51,010 --> 00:05:54,610 However we have the architecture is the only difference. 67 00:05:54,670 --> 00:06:04,600 So if you'll notice we have after our begin or see out is equal to r c and value added with our X input 68 00:06:04,690 --> 00:06:13,360 exclusive or with our Y input and the result of that is logically ored with the result of the X and 69 00:06:13,480 --> 00:06:23,260 logical ended with the Y input and are some r s value is equal to our X exclusively or with R Y which 70 00:06:23,260 --> 00:06:25,980 is exclusively or with R C in. 71 00:06:26,080 --> 00:06:30,510 And so this is doing the same exact thing as a behavioral style. 72 00:06:30,520 --> 00:06:35,650 This is going to result in the same exact circuitry except in our data flow we're telling exactly which 73 00:06:35,650 --> 00:06:42,340 dates to use that are behavioral synthesizer is determining the gates we're using with a structural 74 00:06:42,340 --> 00:06:43,320 architecture. 75 00:06:43,480 --> 00:06:48,490 This is where you will contain component instantiations of previous designs you've worked on. 76 00:06:48,490 --> 00:06:53,770 This is typically if you have a more complex design or a system where you have a lot of stuff going 77 00:06:53,770 --> 00:06:57,130 on you may have a B and C already completed. 78 00:06:57,220 --> 00:07:01,930 So you pull those designs in and add some of your own custom logic and kind of internally wire them 79 00:07:01,930 --> 00:07:02,830 together. 80 00:07:03,160 --> 00:07:06,740 And we also may include a little bit dataflow style in here. 81 00:07:06,970 --> 00:07:12,660 This is when you're working with complex designs or a lot of times is a very common way of doing things. 82 00:07:13,920 --> 00:07:16,000 So let's take a look at a structural example. 83 00:07:16,050 --> 00:07:25,280 So at a top level we're still doing a full adder and a full outer is created by as is 2 1/2 adder's 84 00:07:25,560 --> 00:07:31,350 So we have a half adder makes the whole design file which you can see we have the half after half an 85 00:07:31,340 --> 00:07:33,380 hour and an OR gate. 86 00:07:33,480 --> 00:07:41,100 And with these 2 1/2 hours in or DAY we're going to create a structural design or FLATTR so with our 87 00:07:41,100 --> 00:07:49,350 structural example we have the library and entity which is the same exact as our data flow and our behavioral 88 00:07:49,350 --> 00:07:50,280 styles. 89 00:07:50,280 --> 00:07:57,120 Now the structural style we have this component instantiation we're instantiating a half after which 90 00:07:57,120 --> 00:08:07,290 contains a Kerry s a and b and we have our internal signals which are half some carry and carry two. 91 00:08:07,500 --> 00:08:11,220 And then what we're doing is we're in stanching or half at or twice. 92 00:08:11,250 --> 00:08:19,140 So we have half hour one and half hour or two and we're assigning these values carry one half some x 93 00:08:19,320 --> 00:08:27,510 y carry to X half some and C in and if you'll notice you look at the carry one and carry two and half 94 00:08:27,510 --> 00:08:34,470 some and how they correlate with the top view block diagram and then we also have a or gate where we're 95 00:08:34,470 --> 00:08:37,070 offering our carry one with our carry two. 96 00:08:37,090 --> 00:08:39,660 And so this is how you implement structural design. 97 00:08:39,650 --> 00:08:46,100 We have this half hour design which is located off somewhere else a separate Be it showed as I M-file. 98 00:08:46,230 --> 00:08:49,120 And we're doing a good point instantiation and it together. 99 00:08:50,450 --> 00:08:53,420 Now you've covered all the different aspects of the design. 100 00:08:53,420 --> 00:08:55,200 Let's start looking at some examples.