WEBVTT 00:12.360 --> 00:19.040 Welcome to the VHDL design structure lecture in this lecture I'm going to explain the structure of HDL 00:19.050 --> 00:19.860 design. 00:21.600 --> 00:27.660 Micheel design elements let's make them include the following elements we have an entity declaration 00:28.080 --> 00:33.660 which this is used to describe the external interfaces to the outside world and the keywords of an entity 00:33.660 --> 00:38.100 declaration or entity is an end. 00:38.180 --> 00:40.840 And we also have an architectural body. 00:40.890 --> 00:45.950 This describes the internal behavior or the operation of our VHDL design. 00:46.020 --> 00:51.780 And the keywords we're using are architectural body is begin and end. 00:53.410 --> 00:58.210 VHDL entities contain both courts and generics. 00:58.210 --> 01:06.040 A port is what specifically used to indicate our inputs and outputs of our design and the generic is 01:06.040 --> 01:10.080 used to more like a replacement or a constant. 01:10.090 --> 01:13.160 So for example we have entity. 01:13.300 --> 01:17.850 Us Are we have a generic and a core are generic. 01:17.850 --> 01:21.910 We're calling data wit and we're setting it to an integer value of eight. 01:22.030 --> 01:27.330 So anywhere where we see the value data wit we can replace that with a value of 8. 01:27.360 --> 01:33.520 And so in your design it makes it easy because this tells us the size of our input and the size of our 01:33.520 --> 01:37.490 output signals a Their output signal and our input signal. 01:37.990 --> 01:43.210 So we plan to change data with in one spot if we want to make it the data within 10. 01:43.240 --> 01:48.380 We just replace it once and our design is now a 10 bit universal shift register. 01:48.820 --> 01:50.720 And for our port. 01:50.930 --> 01:53.130 As I said it's our inputs and outputs. 01:53.230 --> 01:56.760 So we have an architecture which contains signals and everything else. 01:56.770 --> 02:03.310 But what we physically see or what we map is our port values. 02:04.540 --> 02:09.850 Now ports each member has a specific mode and data type. 02:09.850 --> 02:18.910 So the different modes are in which is an input only we have out which is an output only now which is 02:18.910 --> 02:22.420 a bidirectional it can be an input or an output. 02:22.600 --> 02:23.700 And we have a buffer. 02:23.860 --> 02:29.010 And this is an output port that can also be read from inside the architectural body. 02:29.090 --> 02:35.140 Now so for example we you can see we have a data flow to flatter our port which contains that test which 02:35.140 --> 02:41.620 is an output and then the data type which is a standard logic and R C out which we define as an output 02:41.670 --> 02:49.690 with the keyword out the day type of Statter logic and then our X Y and C in our all declaratives inputs 02:50.070 --> 02:53.980 with the keyword in and they're all the same data type of standard logic 02:56.360 --> 02:59.360 generics they do not contain a mode. 02:59.390 --> 03:06.010 They only contain a data type and they're used as a means of passing specific information into the entity. 03:06.330 --> 03:09.070 And neither typically think of them just like a consonant. 03:09.080 --> 03:15.110 So if you have a design and you want to use a value you can pass in as a generic. 03:15.140 --> 03:19.820 You have to change it once and then alter your design you can reference that generic without having 03:19.820 --> 03:26.330 to change multiple lines of code as you come up with more complex and better designs. 03:27.140 --> 03:33.890 The VHDL architecture body This consists of concurrent signal assignment statements process statements 03:33.980 --> 03:36.410 and component instantiation of statements. 03:36.410 --> 03:38.600 This is the whole meaning design. 03:38.600 --> 03:42.770 This is where you're specifying how you want your design to operate. 03:42.770 --> 03:48.430 So you had your entity which tells you design what are my inputs and what are my outputs. 03:48.590 --> 03:54.320 You have the architecture body which says OK I'm taking you then puts in what kind of processing or 03:54.320 --> 03:55.920 what am I doing to the inputs. 03:56.000 --> 04:00.910 And then I specify based on my inputs and internal signals and everything else. 04:00.950 --> 04:02.390 What are my outputs. 04:02.390 --> 04:06.610 So the architecture body is the brains the processing everything that's happening. 04:06.620 --> 04:10.560 We're taking the inputs and we're specifying what we're doing with the outputs. 04:10.880 --> 04:14.330 So if you look we have how do we specify architecture. 04:14.360 --> 04:23.480 Body we have architecture data flow of Flader which flatter one is the same name or entity this or specifying 04:23.490 --> 04:25.380 OK with that entity. 04:25.400 --> 04:28.170 Here is the architecture of that entity. 04:28.330 --> 04:35.320 Now we have the key word is and again this is like the decoration of our architecture body. 04:35.570 --> 04:37.000 Then we have the statement. 04:37.010 --> 04:44.060 This is where we put the concurrent signal assignments the process statements and the component instantiations. 04:44.090 --> 04:45.660 This is where all that goes. 04:45.700 --> 04:51.200 And so in a statement this is where all of the inner workings are taking place we're specifying our 04:51.200 --> 04:54.920 output C out and S given our inputs. 04:54.920 --> 05:03.710 We have to see in X and Y and so given those inputs we're telling it what the outputs are. 05:03.750 --> 05:06.510 Now you're familiar with the structure of VHDL design. 05:06.510 --> 05:09.390 Next we'll look into the different architecture styles.