1 00:00:12,360 --> 00:00:19,040 Welcome to the VHDL design structure lecture in this lecture I'm going to explain the structure of HDL 2 00:00:19,050 --> 00:00:19,860 design. 3 00:00:21,600 --> 00:00:27,660 Micheel design elements let's make them include the following elements we have an entity declaration 4 00:00:28,080 --> 00:00:33,660 which this is used to describe the external interfaces to the outside world and the keywords of an entity 5 00:00:33,660 --> 00:00:38,100 declaration or entity is an end. 6 00:00:38,180 --> 00:00:40,840 And we also have an architectural body. 7 00:00:40,890 --> 00:00:45,950 This describes the internal behavior or the operation of our VHDL design. 8 00:00:46,020 --> 00:00:51,780 And the keywords we're using are architectural body is begin and end. 9 00:00:53,410 --> 00:00:58,210 VHDL entities contain both courts and generics. 10 00:00:58,210 --> 00:01:06,040 A port is what specifically used to indicate our inputs and outputs of our design and the generic is 11 00:01:06,040 --> 00:01:10,080 used to more like a replacement or a constant. 12 00:01:10,090 --> 00:01:13,160 So for example we have entity. 13 00:01:13,300 --> 00:01:17,850 Us Are we have a generic and a core are generic. 14 00:01:17,850 --> 00:01:21,910 We're calling data wit and we're setting it to an integer value of eight. 15 00:01:22,030 --> 00:01:27,330 So anywhere where we see the value data wit we can replace that with a value of 8. 16 00:01:27,360 --> 00:01:33,520 And so in your design it makes it easy because this tells us the size of our input and the size of our 17 00:01:33,520 --> 00:01:37,490 output signals a Their output signal and our input signal. 18 00:01:37,990 --> 00:01:43,210 So we plan to change data with in one spot if we want to make it the data within 10. 19 00:01:43,240 --> 00:01:48,380 We just replace it once and our design is now a 10 bit universal shift register. 20 00:01:48,820 --> 00:01:50,720 And for our port. 21 00:01:50,930 --> 00:01:53,130 As I said it's our inputs and outputs. 22 00:01:53,230 --> 00:01:56,760 So we have an architecture which contains signals and everything else. 23 00:01:56,770 --> 00:02:03,310 But what we physically see or what we map is our port values. 24 00:02:04,540 --> 00:02:09,850 Now ports each member has a specific mode and data type. 25 00:02:09,850 --> 00:02:18,910 So the different modes are in which is an input only we have out which is an output only now which is 26 00:02:18,910 --> 00:02:22,420 a bidirectional it can be an input or an output. 27 00:02:22,600 --> 00:02:23,700 And we have a buffer. 28 00:02:23,860 --> 00:02:29,010 And this is an output port that can also be read from inside the architectural body. 29 00:02:29,090 --> 00:02:35,140 Now so for example we you can see we have a data flow to flatter our port which contains that test which 30 00:02:35,140 --> 00:02:41,620 is an output and then the data type which is a standard logic and R C out which we define as an output 31 00:02:41,670 --> 00:02:49,690 with the keyword out the day type of Statter logic and then our X Y and C in our all declaratives inputs 32 00:02:50,070 --> 00:02:53,980 with the keyword in and they're all the same data type of standard logic 33 00:02:56,360 --> 00:02:59,360 generics they do not contain a mode. 34 00:02:59,390 --> 00:03:06,010 They only contain a data type and they're used as a means of passing specific information into the entity. 35 00:03:06,330 --> 00:03:09,070 And neither typically think of them just like a consonant. 36 00:03:09,080 --> 00:03:15,110 So if you have a design and you want to use a value you can pass in as a generic. 37 00:03:15,140 --> 00:03:19,820 You have to change it once and then alter your design you can reference that generic without having 38 00:03:19,820 --> 00:03:26,330 to change multiple lines of code as you come up with more complex and better designs. 39 00:03:27,140 --> 00:03:33,890 The VHDL architecture body This consists of concurrent signal assignment statements process statements 40 00:03:33,980 --> 00:03:36,410 and component instantiation of statements. 41 00:03:36,410 --> 00:03:38,600 This is the whole meaning design. 42 00:03:38,600 --> 00:03:42,770 This is where you're specifying how you want your design to operate. 43 00:03:42,770 --> 00:03:48,430 So you had your entity which tells you design what are my inputs and what are my outputs. 44 00:03:48,590 --> 00:03:54,320 You have the architecture body which says OK I'm taking you then puts in what kind of processing or 45 00:03:54,320 --> 00:03:55,920 what am I doing to the inputs. 46 00:03:56,000 --> 00:04:00,910 And then I specify based on my inputs and internal signals and everything else. 47 00:04:00,950 --> 00:04:02,390 What are my outputs. 48 00:04:02,390 --> 00:04:06,610 So the architecture body is the brains the processing everything that's happening. 49 00:04:06,620 --> 00:04:10,560 We're taking the inputs and we're specifying what we're doing with the outputs. 50 00:04:10,880 --> 00:04:14,330 So if you look we have how do we specify architecture. 51 00:04:14,360 --> 00:04:23,480 Body we have architecture data flow of Flader which flatter one is the same name or entity this or specifying 52 00:04:23,490 --> 00:04:25,380 OK with that entity. 53 00:04:25,400 --> 00:04:28,170 Here is the architecture of that entity. 54 00:04:28,330 --> 00:04:35,320 Now we have the key word is and again this is like the decoration of our architecture body. 55 00:04:35,570 --> 00:04:37,000 Then we have the statement. 56 00:04:37,010 --> 00:04:44,060 This is where we put the concurrent signal assignments the process statements and the component instantiations. 57 00:04:44,090 --> 00:04:45,660 This is where all that goes. 58 00:04:45,700 --> 00:04:51,200 And so in a statement this is where all of the inner workings are taking place we're specifying our 59 00:04:51,200 --> 00:04:54,920 output C out and S given our inputs. 60 00:04:54,920 --> 00:05:03,710 We have to see in X and Y and so given those inputs we're telling it what the outputs are. 61 00:05:03,750 --> 00:05:06,510 Now you're familiar with the structure of VHDL design. 62 00:05:06,510 --> 00:05:09,390 Next we'll look into the different architecture styles.