WEBVTT 00:12.890 --> 00:19.580 Welcome to the VHDL processes and concurrent statements lecture in this lecture I'm going to talk about 00:19.580 --> 00:24.590 processes and VHDL and concurrent signal assignments. 00:24.680 --> 00:32.090 What is a VHDL process in which a process is a way we set up to determine how do we want to evaluate 00:32.090 --> 00:33.200 certain signals. 00:33.260 --> 00:38.310 That process is evaluated when a signal and a sensitivity list has changed state. 00:38.570 --> 00:45.950 So any signal we put in the sensitivity list of our process if it goes from a high to a low or if we 00:45.950 --> 00:50.210 have a sound logic vector in there any one of those go from a high to a low. 00:50.210 --> 00:56.420 That process is evaluated and Ameche processes contains several parts. 00:56.450 --> 01:03.200 We have to name the sensitivity list the begin statement and the end process statement. 01:03.200 --> 01:06.480 The name is what we use to name our process. 01:06.530 --> 01:13.070 We have multiple processes and a large design the name is just kind of used to help organize and structure 01:13.070 --> 01:14.160 for talking with someone. 01:14.300 --> 01:20.930 You can just define that process and also the sensitivity list is what we use to determine when that 01:20.930 --> 01:26.020 process gets evaluated the begin statement tells us when we want to actually. 01:26.060 --> 01:27.220 Where does our process start. 01:27.230 --> 01:32.980 So we have our process we can instantiate a variable and then we tell it to begin. 01:33.110 --> 01:39.530 And we have our end process statement so take a look at a VHDL process. 01:39.530 --> 01:46.290 We have our name which we're calling state underscore PRC or short from process. 01:46.310 --> 01:52.610 And then we give it the semi-colon and we call it a process and our sensitivity list and the sensitivity 01:52.610 --> 01:56.870 list we have a clock which is a common signal to put in your process. 01:57.080 --> 02:02.540 But what that means is that clock as it's toggling from low to high to high to low. 02:02.690 --> 02:06.670 Every time it makes a transition so it starts out low and goes high. 02:06.770 --> 02:12.780 This process gets evaluated and then as time goes low this process gets evaluated again. 02:12.890 --> 02:19.160 And so then we have our begin statement where we actually start the evaluation process and inside our 02:19.160 --> 02:26.300 process we just have a simple if else statement where if it's the rising edge of our clock then we're 02:26.300 --> 02:32.060 going to check the second IF statement where if a reset is equal to zero then we're setting our state 02:32.120 --> 02:36.740 value to a net else our state value is equal to next state. 02:36.890 --> 02:38.570 And so every time our clock. 02:38.690 --> 02:45.440 Once it's on the rising edge we'll evaluate the if else and if statement if it's the falling edge it's 02:45.440 --> 02:47.620 going to check that if rising edge clock. 02:47.810 --> 02:53.000 And that's not the case so she is going to exit out of that process and you don't have to put a clock 02:53.030 --> 02:58.730 you can put a stat logic vector an integer or any signal inside that process to determine when you want 02:58.730 --> 03:07.110 to evaluate that now it's about the concurrent signal assignments a single assignments are used to assign 03:07.110 --> 03:13.860 a specific value to a signal inside your VHDL design signals can be assigned a set of values such as 03:13.860 --> 03:21.280 a one or a zero or you can have an integer value that you set 1 2 3 4 5 6 so and so forth. 03:21.690 --> 03:26.850 And the big thing you know about signal assignments is that these are concurrent. 03:26.850 --> 03:36.570 So if I have at the very top of my design a equals one and then I have C equals zero a equal get set 03:36.570 --> 03:40.350 to one at the same exact time that C gets set to zero. 03:40.350 --> 03:41.690 These things happen concurrently. 03:41.700 --> 03:42.830 There is no order of. 03:42.930 --> 03:45.120 This happens first this happens second. 03:45.150 --> 03:47.060 It's the same exact time. 03:47.490 --> 03:50.970 So let's take a look at how we do a concurrent signal assignment. 03:51.210 --> 03:59.340 We have our next state is being set to value a state so rapid that we know that next state and state 03:59.460 --> 04:00.970 have to be the same data type. 04:01.110 --> 04:06.060 We cannot assign to different data types one of one data type to one of another. 04:06.060 --> 04:07.960 They have to be the same type. 04:08.220 --> 04:09.180 We have our shift. 04:09.180 --> 04:16.890 We're setting to the value of zero as we all are ADD flow data and data read a data ready are all being 04:16.890 --> 04:19.560 set to the value zero. 04:19.560 --> 04:26.130 Now the important thing to know is at the exact same time that next state is getting the value of state 04:26.520 --> 04:28.710 data ready is getting a value of zero. 04:28.710 --> 04:32.740 So I could rearrange this order and the outputs are going to be the same. 04:32.760 --> 04:35.230 My design is going to act the same. 04:35.250 --> 04:37.440 All these happened simultaneously. 04:37.430 --> 04:41.760 There's no order where one happens and the next one happens so on and so forth. 04:41.840 --> 04:44.910 And that's kind of a huge thing I'm working with FPGA and VHDL. 04:44.940 --> 04:47.730 We had this advantage of parallelism. 04:47.730 --> 04:54.550 I can say I want this to happen at the same exact time this is happening and they will now that we have 04:54.550 --> 04:58.570 finished the VHDL syntax section let's begin looking at the cutting structure.