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Welcome to the VHDL processes and concurrent statements lecture in this lecture I'm going to talk about

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processes and VHDL and concurrent signal assignments.

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What is a VHDL process in which a process is a way we set up to determine how do we want to evaluate

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certain signals.

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That process is evaluated when a signal and a sensitivity list has changed state.

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So any signal we put in the sensitivity list of our process if it goes from a high to a low or if we

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have a sound logic vector in there any one of those go from a high to a low.

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That process is evaluated and Ameche processes contains several parts.

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We have to name the sensitivity list the begin statement and the end process statement.

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The name is what we use to name our process.

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We have multiple processes and a large design the name is just kind of used to help organize and structure

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for talking with someone.

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You can just define that process and also the sensitivity list is what we use to determine when that

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process gets evaluated the begin statement tells us when we want to actually.

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Where does our process start.

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So we have our process we can instantiate a variable and then we tell it to begin.

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And we have our end process statement so take a look at a VHDL process.

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We have our name which we're calling state underscore PRC or short from process.

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And then we give it the semi-colon and we call it a process and our sensitivity list and the sensitivity

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list we have a clock which is a common signal to put in your process.

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But what that means is that clock as it's toggling from low to high to high to low.

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Every time it makes a transition so it starts out low and goes high.

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This process gets evaluated and then as time goes low this process gets evaluated again.

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And so then we have our begin statement where we actually start the evaluation process and inside our

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process we just have a simple if else statement where if it's the rising edge of our clock then we're

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going to check the second IF statement where if a reset is equal to zero then we're setting our state

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value to a net else our state value is equal to next state.

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And so every time our clock.

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Once it's on the rising edge we'll evaluate the if else and if statement if it's the falling edge it's

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going to check that if rising edge clock.

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And that's not the case so she is going to exit out of that process and you don't have to put a clock

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you can put a stat logic vector an integer or any signal inside that process to determine when you want

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to evaluate that now it's about the concurrent signal assignments a single assignments are used to assign

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a specific value to a signal inside your VHDL design signals can be assigned a set of values such as

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a one or a zero or you can have an integer value that you set 1 2 3 4 5 6 so and so forth.

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And the big thing you know about signal assignments is that these are concurrent.

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So if I have at the very top of my design a equals one and then I have C equals zero a equal get set

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to one at the same exact time that C gets set to zero.

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These things happen concurrently.

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There is no order of.

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This happens first this happens second.

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It's the same exact time.

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So let's take a look at how we do a concurrent signal assignment.

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We have our next state is being set to value a state so rapid that we know that next state and state

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have to be the same data type.

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We cannot assign to different data types one of one data type to one of another.

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They have to be the same type.

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We have our shift.

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We're setting to the value of zero as we all are ADD flow data and data read a data ready are all being

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set to the value zero.

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Now the important thing to know is at the exact same time that next state is getting the value of state

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data ready is getting a value of zero.

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So I could rearrange this order and the outputs are going to be the same.

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My design is going to act the same.

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All these happened simultaneously.

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There's no order where one happens and the next one happens so on and so forth.

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And that's kind of a huge thing I'm working with FPGA and VHDL.

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We had this advantage of parallelism.

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I can say I want this to happen at the same exact time this is happening and they will now that we have

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finished the VHDL syntax section let's begin looking at the cutting structure.