1 00:00:01,290 --> 00:00:07,500 Or working with the HD you know a lot of people tend to think that we're programming and actually we're 2 00:00:07,500 --> 00:00:07,860 not. 3 00:00:07,890 --> 00:00:15,850 So what I want to show you is here is a project I have opened Microsoft Visual Studios to see C++ project 4 00:00:16,080 --> 00:00:24,300 and essentially what's going on is I have a for loop that is we have an integer I am or looping through 5 00:00:24,300 --> 00:00:28,370 five times and we're just outputting the value of the variable line. 6 00:00:28,600 --> 00:00:33,570 It's all going to go ahead run this is to show you what this is what type a for loop will look like 7 00:00:33,840 --> 00:00:36,340 and a software type of environment. 8 00:00:36,750 --> 00:00:40,940 Do the buggy build it. 9 00:00:40,950 --> 00:00:42,500 Yes we do. 10 00:00:42,540 --> 00:00:43,810 So we're going to build in the bug. 11 00:00:43,840 --> 00:00:52,620 And as you can see our output just shows us that the value of pi changes from 0 1 2 3 4 and it's just 12 00:00:52,620 --> 00:00:54,080 all happened sequentially. 13 00:00:54,120 --> 00:00:59,910 So when you think of a for loop and software if you have a software background that you know it loops 14 00:00:59,910 --> 00:01:03,370 through the number of times based on the parameters you give it. 15 00:01:03,470 --> 00:01:08,970 It will loops through X number of times number of times and we go from zero to four which gives us five 16 00:01:08,970 --> 00:01:11,960 different five times the loop through. 17 00:01:11,970 --> 00:01:15,560 So if we do that VHDL How does that how is that different. 18 00:01:15,560 --> 00:01:18,140 Because in VHDL they have four words. 19 00:01:18,150 --> 00:01:21,370 So let's look in Xilinx. 20 00:01:21,520 --> 00:01:28,260 Here is a I'm not going to go through how to create this just to show you real quick what a for loop 21 00:01:28,350 --> 00:01:29,990 image will look like. 22 00:01:30,090 --> 00:01:36,150 And in the syntax section we'll go ahead and cover exactly what a for loop needs to require and everything 23 00:01:36,150 --> 00:01:36,980 like that. 24 00:01:36,990 --> 00:01:44,150 So just looking at lines Forty-Eight in through line 50 We have a for loop where we have a variable 25 00:01:44,160 --> 00:01:50,390 I am looping from 0 to 4 which is the same as the supposed possible. 26 00:01:50,400 --> 00:02:00,060 We looked at and we're taking our variable A and saying it's equal to B and C.. 27 00:02:00,300 --> 00:02:03,900 So if we're going to have when we go ahead and synthesize this and we're going to show you the real 28 00:02:03,900 --> 00:02:09,260 time logic schematic and so what that is this is just showing you the hardware that it generates. 29 00:02:09,480 --> 00:02:15,900 So when you run this if you put this on an FPGA where it will look like is this right here you have 30 00:02:16,200 --> 00:02:22,460 your top file one which is just a VHDL file and essentially system and gate that you have for inputs 31 00:02:22,820 --> 00:02:28,940 from your C for inputs from your B just two different standard logic vectors and output. 32 00:02:28,980 --> 00:02:34,650 So it's not actually sequentially going through it's just all happening simultaneous simultaneously. 33 00:02:34,740 --> 00:02:36,610 You have these two inputs. 34 00:02:36,660 --> 00:02:42,780 They are adding together to give you an output and so that is kind of the difference between VHDL and 35 00:02:42,780 --> 00:02:49,230 software and software you're modifying the values of variables in hardware you're describing. 36 00:02:49,230 --> 00:02:53,280 The fact is that you know you're describing the actual hardware. 37 00:02:53,280 --> 00:02:57,690 So let's take a look and see what a VHDL hardware. 38 00:02:57,690 --> 00:03:02,810 So let's say we have a digital logic circuit we want to generate in VHDL like laugh. 39 00:03:02,840 --> 00:03:14,460 We have our inputs A B and C or the inputs A and B and the value of that their input C invert value 40 00:03:14,580 --> 00:03:19,380 and output D and so on the right is the VHDL equivalent of that. 41 00:03:19,380 --> 00:03:26,490 So if we would take the program of the right and put that into the Xilinx IAC tool and go ahead and 42 00:03:26,880 --> 00:03:31,500 generate the program it would actually generate the hardware that you see on the left. 43 00:03:31,500 --> 00:03:36,580 The digital logic circuit will take it in month that inside of the FPGA. 44 00:03:36,660 --> 00:03:41,790 So that is what the HGL is doing we're centrally describing exactly how we want the hardware to work 45 00:03:41,790 --> 00:03:47,400 we're telling it what are the inputs what are the outputs and what's going on between what are we doing 46 00:03:47,400 --> 00:03:49,470 with those inputs to generate the output.