WEBVTT 00:13.290 --> 00:19.660 Welcome to the if statement case statement lecture in this lecture I'm going to talk about the syntax 00:19.690 --> 00:25.570 and workings of an IF statement as well as a case statement in the VHDL language. 00:25.690 --> 00:28.710 First let's start off by talking about statements. 00:28.730 --> 00:35.710 Their statements are conditional statements that must either evaluate to a true or false condition with 00:35.710 --> 00:36.340 their statements. 00:36.340 --> 00:42.730 We can also have an else statement or clause where the statement does not need to evaluate to TRUE or 00:42.730 --> 00:43.680 FALSE. 00:43.820 --> 00:50.260 If the first condition is not true or does not evaluate to true then we will go ahead and evaluate the 00:50.260 --> 00:51.730 else clause. 00:51.730 --> 00:55.310 Or you can also have an if and if statement. 00:55.350 --> 01:03.760 Meaning if the statement is true or condition is it true you will evaluate the expression nested inside 01:03.760 --> 01:04.790 of your statement. 01:04.840 --> 01:06.640 We'll go through some examples. 01:06.740 --> 01:13.650 A keyword soon if statement are if then else else an end. 01:14.170 --> 01:20.920 And VHDL supports nested if statements so you can have an if statement in a and then another if statement 01:20.980 --> 01:25.450 inside of that and just kind of keep nesting through. 01:25.480 --> 01:28.500 So let's walk through a couple if statement examples. 01:28.630 --> 01:37.180 The first example we have fith enable is equal to 1 then our result is equal to A else. 01:37.180 --> 01:40.770 Our result is equal to others zero. 01:40.780 --> 01:46.190 So if you think no one our conditional statement and table is equal to one. 01:46.330 --> 01:49.690 This is a conditional statement either it's true or false. 01:49.720 --> 01:56.650 If our Nabl is a one to lose all is equal to a far Nabl is zero a result is equal to all the values 01:56.650 --> 01:58.720 are set to zero. 01:58.720 --> 02:00.980 So a couple things we get no result. 02:01.060 --> 02:01.570 A. 02:01.630 --> 02:04.180 They must be the same data type. 02:04.180 --> 02:10.520 Now we know because a result is beings with the keyword in the else clause being the other set to zero. 02:10.540 --> 02:16.530 We know that result and they have to be either standard logic Nectars signed or unsigned data types. 02:16.560 --> 02:18.800 And so this is a valid if statement. 02:19.330 --> 02:22.250 Let's take a look at another example we have. 02:22.420 --> 02:27.710 If enable plus check then result is equal to A and f.. 02:27.790 --> 02:32.740 Now this is an if and if statement which is valid. 02:32.740 --> 02:36.570 However our conditional statement does not equal to true or false. 02:36.610 --> 02:42.420 We just have a label plus check that does not equal a 0 or 1 or true or false. 02:42.610 --> 02:44.140 That can be any value. 02:44.140 --> 02:50.500 So this is an invalid if statement for that reason because that conditional statement is not a true 02:50.500 --> 02:51.820 or false. 02:51.820 --> 02:58.810 Now let's take another look if we have an able is equal to a zero then result is equal to A and end 02:58.810 --> 02:59.100 it. 02:59.110 --> 03:05.810 So here we do not have the else clause just the if and if and so this is a valid statement. 03:08.440 --> 03:14.550 What if statements you can do multiple else if we have there is really no limit. 03:14.560 --> 03:17.600 You can do and if else if else if else. 03:17.950 --> 03:18.950 And then an else. 03:19.060 --> 03:28.300 So for example we have if a in the zero the leason if I get that element of that vector is equal to 03:28.330 --> 03:32.490 1 then or encode is equal to zero zero zero. 03:32.650 --> 03:38.320 And if you look through all the else if we have different values if A and one is equal to one then our 03:38.320 --> 03:48.340 own code is 0 0 1 all the way down to LCF or 8 and 7 is equal to a 1 that are code is equal to 1 1 1. 03:48.410 --> 03:50.910 Then we also have the else if none of the. 03:50.920 --> 03:57.620 Or else if statements evaluate to a true then we are going to go and evaluate our statement. 03:57.640 --> 04:05.920 So if our AA and 0 through 7 if none of those are equal to the 1 then our code is going to have the 04:05.920 --> 04:08.760 output of an X or an undefined. 04:09.040 --> 04:15.670 In VHDL language now important thing to note with the LCF statements in VHDL you would think that it 04:15.670 --> 04:19.310 would be spelled like well as e-space. 04:19.370 --> 04:27.160 If however that's not the case it is a class which is slightly confusing but make sure to note that 04:27.190 --> 04:33.670 if you type it you see space I-F it will give you an air and that's an invalid syntax. 04:35.110 --> 04:43.410 So spoke about the case statements in VHDL a case statement checks and inputs against multiple cases. 04:43.420 --> 04:49.360 And the key words for a case statement are case when and and Case No. 04:49.390 --> 04:55.180 When you have a case statement it's important to note the direction of your equals and your arrow sign 04:55.270 --> 05:01.510 as well as your arrow in equals when you're working with Case statements every possible option must 05:01.510 --> 05:04.790 be covered for use the other's keyword. 05:05.230 --> 05:07.210 So conditions cannot overlap. 05:07.210 --> 05:12.200 If I have a case is equal between 1 and 3. 05:12.220 --> 05:17.770 No my next case is equal to a two that becomes invalid because now they overlap. 05:17.770 --> 05:24.010 I have a one in three of my value the two my one in three that I equate to true and my two is in Iowa 05:24.220 --> 05:24.870 true. 05:25.180 --> 05:28.760 So for example we have our case. 05:28.750 --> 05:36.610 We're taking our value inputs and we're saying when our inputs is 0 0 0 the outputs it's going to be 05:36.600 --> 05:38.050 equal to zero zero. 05:38.140 --> 05:44.560 And if we keep following through we have the same type of situation going on we have when our inputs 05:44.920 --> 05:50.350 is equal to 0 0 1 our output is equal to zero one. 05:50.440 --> 05:56.560 And if you notice we cover all different conditions from 0 0 0 to 1 1 1. 05:56.650 --> 06:01.610 We also have the others which is really good to put whenever you have a case statement. 06:01.720 --> 06:03.820 I recommend you always have an other statement. 06:03.820 --> 06:10.780 That way if you forget to cover a certain case that could happen you want to make sure that you give 06:10.780 --> 06:17.110 yourself this kind of an error detection or back false safety function where in this case our outputs 06:17.470 --> 06:19.400 were does give us the Xs or the undefine. 06:19.420 --> 06:24.460 So when you're simulating if you ever see an X or undefined when you're outputs you know that something 06:24.460 --> 06:28.900 is going on with your inputs and you have an air. 06:29.150 --> 06:33.950 If you look at the if statements in the case statements you notice that they're relatively similar. 06:34.070 --> 06:40.520 And if we have a function we can implement or do the same thing in an IF statement Bearse a case statement. 06:40.520 --> 06:45.640 However the key difference is that an IF statement infers priority. 06:45.800 --> 06:48.420 This is because the first statement is true. 06:48.470 --> 06:53.210 It will evaluate that expression and then ignore the rest of the LCS. 06:53.210 --> 06:58.970 However with a case statement we have to cover every possible case and so there is no priority in a 06:58.970 --> 07:00.020 case statement. 07:00.020 --> 07:07.430 You cannot have an overlapping situation where and if else if statement you could have overlapping conditions. 07:07.430 --> 07:11.630 And so with the case statement every single case has the same exact priority. 07:11.660 --> 07:16.100 And so that's just the big difference between a statement or case statement and with an if statement 07:16.100 --> 07:20.170 you do not have to cover every single possibility like you do with the case. 07:22.010 --> 07:24.880 Now you're familiar with F statements and case statements. 07:24.920 --> 07:28.020 Let's start looking at different loops in a VHDL language.