VHDL Syntax Introduction
In this article I am going to introduce and explain the syntax of the VHDL language. When working with VHDL there are various different keywords as in other languages. A list below contains multiple keywords used in the VHDL language.
| Syntax | What does it do |
| -- | VHDL Comment |
| := | Assigns an initial value |
| => | Assignsobject on right value of object on left |
| <= | Assignsobject on left value of object on right |
| ; | Indicatesend of line |
| : | Used to Specifya data type for an Object |
| ‘1’ | Value of a std_logic |
| “100” | Value of a std_logic_vector(3 bits) |
| Rising_edge | Refers to the rising edge of a signal |
| Entity | a primary design unit |
| Architecture | A secondary design unit |
| Port | interface definition, also port map |
| Generic | introduces generic part of a declaration |
| Signal | declaration that an object is a signal |
| Constant | declares an identifier to be read only |
| Begin | start of a begin end pair |
| End | part of many statements, may be followed by word and id |
| Others | Assigns all unpicked bits in a std_logic_vector, unsigned, or signed data type |
These keywords are used in conjunction with different logical statements to produce hardware designs.