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Here's the behavioral for after you know slicking line one you'll notice a comment the two dashes and

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then you look at the text afterwards.

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It isn't brain which is indicated that it's a comment.

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So we moved down to the next line line 2 and 3 2 is we're saying that we're going to use the library

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the Tripoli library and then line 3 is telling us to use a standard logic 1 1 6 for all.

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So what that tells us is that allows us to use the data type standard logic and standard logic vector

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Rebello that you can see if we have an entity which is called for water too.

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And if you'll notice on line 14 the behavior named the architecture behavior and the of the word tells

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us that water too.

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And you can notice the different keywords in VHDL when you're using Notepad plus plus the keywords are

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highlighted in blue or green or yellow gray that just highlight different keywords to different colors.

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And we look at our outputs we have S and see out which are the data types and logic just meaning that

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there they're either a 1 or zero and it only a single bit.

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If you look at the inputs X Y and C and we notice that there a one bit standard logic as well that we

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have on line 16 and 17 the out there signals which just means that they're internal to our FPGA they

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don't actually get mapped to anything on the board and we call them inputs and outputs.

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Now if you notice the signal inputs has is a standard logic factor which mean two down to zero which

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gives us three bits.

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And if you notice we have three inputs on a report.

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So essentially what we're doing is we're mapping our inputs to the three inputs we have.

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We're taking every inputs x y c underscore n and we're mapping them or input our signal inputs and we'll

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do the same thing with the outputs.

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We're just going to generate the outputs and then we map the output signal to the signals declared and

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write to you and then we have the keyword begin to move down.

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We have another comment the dash dash creates another comment comments so if I start typing here someone

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put dash dash and all of sudden it turns green because it indicates he knows that that is a comment.

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So here we have our inputs with arrow equals what we're doing is taking the inputs see an X and Y and

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concatenating them together which is indicated with the single ampersand.

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So we're taking our why ampersand and with our X ampersand and with RCN which concatenates all three

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of those which are each a single standard logic value two inputs which is indicated as a standard logic

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factor two down to zero.

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And so this math adds up and it'll work out OK in our C hours.

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We could do it for our outputs.

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We could do a ampersand to concatenate them.

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This is just showing you a different way of doing that by using the parentheses to indicate that the

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outputs are one which would be our most significant bit is being mapped to our Out in our output zero

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which is our least and if it can get that being added to our pasts and here we have a process named

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after process and that there's another keyword.

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The process keyword we have are inputs which is are sensitive to us at any time.

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One of the inputs change you'll notice that this process gets evaluated.

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And it essentially checks the inputs and puts them to the output.

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So you have a begin which is insider process just tells us OK this is where we want to begin in our

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process.

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We have the case keyword which you notice highlighted in blue we have our win which is just this is

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a case statement.

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We're taking our case inputs or checking it against any one of these when values which are on lines

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29 31 33 35 37 9 1 43 and then the other key word is indicating that if none of the inputs match with

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or with any of these when statements this others statement gets evaluated just automatically which in

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this case we only have eight different inputs are going to happen so we can cover all of them.

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However if we were to have say only we cared about three different inputs then we could just have three

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different when statements.

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So is a way to catch everything else.

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Otherwise all air out because it doesn't know what it.

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Now we have in case the word as well as our process in our behavior.

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And that is just some syntax for our VHDL file.