WEBVTT 00:12.820 --> 00:16.040 Well sign the initial values in VHDL. 00:16.150 --> 00:20.140 Are a few examples we can look at to show you how that is done. 00:20.140 --> 00:22.980 So first for line number one. 00:22.990 --> 00:28.870 Just a quick comment to showing you that in your dash dash your comment and your work you know notepad 00:28.870 --> 00:35.130 plus plus as you put the dash dash there you'll notice that your text or anything and type turns green. 00:35.530 --> 00:42.040 So it's pretty neat that when you type a key word and no Paphos Plus how is it what you know that it 00:42.040 --> 00:45.180 recognizes that it's a VHDL file. 00:45.190 --> 00:52.350 So we go ahead and type a type signal in here which is a key word and VHDL and you see this is this. 00:52.470 --> 00:58.690 As soon as I start to type it it shows up there in the dropdown I go and hit enter and then it turns 00:58.690 --> 01:02.300 blue and Kate knows that that's a signal. 01:02.380 --> 01:07.210 And so is the quick way to bet if you're using the Apply Plus plus a key thing to remember if you're 01:07.300 --> 01:14.890 editing a file in Notepad plus plus when you if you go to a file you go ahead and create a new file 01:15.340 --> 01:18.070 and it's going to right away. 01:18.470 --> 01:21.030 It is called a normal text file. 01:21.070 --> 01:26.830 Want to click on language go down to be like VHDL. 01:26.950 --> 01:30.920 Now it will call it the age as I see Hurlburt a script of mine which file. 01:31.120 --> 01:37.130 So now if I type it will pick up signal because I know that that's the key word enter. 01:37.320 --> 01:41.190 It makes it blude indicate that that's a key word. 01:41.260 --> 01:45.060 I'm not going to keep this almanacks of that. 01:45.220 --> 01:47.880 So I will go to our back to our example here. 01:48.100 --> 01:56.470 And so first I have signal A which is a type of integer and I want to give an initial value of 4. 01:56.740 --> 02:07.210 So I have my signal a then I have to do a semi-colon there to a colon to indicate that my data type 02:07.210 --> 02:11.190 which is in the keyword which you notice is is purple. 02:11.380 --> 02:14.510 And then I'll give it a colon equals four. 02:14.530 --> 02:20.530 So what this is doing is I'm saying I have a signal I'm calling it a. 02:20.710 --> 02:25.450 It has an integer type integer an initial value of. 02:25.840 --> 02:31.100 If we move down to three on line with a mindset and we have signal B and. 02:31.240 --> 02:39.040 And do you mean this is a type unsigned with an initial value of 0 0 0 0 because we work with unsigned 02:39.040 --> 02:39.900 and signed. 02:40.030 --> 02:46.960 We have to give it the actual bit values because an integer we can't give it like a 1 or 0 or so on 02:46.960 --> 02:48.270 and so forth. 02:48.270 --> 02:56.950 And so if you look I have signal B my colon indicates the data type unsigned and I give you the keywords 02:57.000 --> 03:05.200 3 down to zero which just means I have an unsigned data type of 4 bits and if you look then I have a 03:05.200 --> 03:11.140 colon equals which I'm going to have the double parentheses which just indicates all the bits. 03:11.140 --> 03:14.350 So it's giving an actually signal B is four bits. 03:14.350 --> 03:22.870 All of them are initialized to zero and B one if you look on line 10 is doing the exact same thing except 03:22.870 --> 03:28.870 we're using the other's key word message to show you you initialize with larger values that you can 03:28.870 --> 03:34.190 see that instead of if I would have liked this is only forbit. 03:34.200 --> 03:35.980 So it's not as big of an issue. 03:36.040 --> 03:45.640 But if this were to be I don't know like a 12 or 24 32 ribbon 64 bit signal instead of putting in 64 03:45.640 --> 03:46.690 zeros in my file. 03:46.690 --> 03:48.060 I can just have this other. 03:48.280 --> 03:55.860 And the zeros there and that keyword will actually initialize a signal be 4 bits wide all with zero. 03:56.370 --> 04:06.700 And if you look down on lines 18 21 with my signal C and C 1 we're doing the exact same thing except 04:06.700 --> 04:17.410 that we're working with these are actually signed values which I have as unsigned because OK I can just 04:17.410 --> 04:23.530 go ahead and read that down to see one on line 21 and move on. 04:23.530 --> 04:33.490 So now signal C and C 1 are doing the same thing as signal B and B one except there sign two types as 04:33.490 --> 04:34.660 opposed unsigned. 04:34.960 --> 04:41.530 And we initialize them in the same way we use the colon equals and give it the value y initialize it 04:41.530 --> 04:45.440 to move down. 04:45.660 --> 04:50.090 Let's look at signing initial values to standard logic sectors. 04:50.250 --> 04:59.400 So we have a signal looking on line 31 we wanted to fine signal a signal and name a as a standard logic 04:59.400 --> 05:06.780 vector data type with an initial value of all ones and count them not there but there's eight ones. 05:06.780 --> 05:08.220 So what we'll do. 05:08.370 --> 05:16.620 We want to put the key signal and type a and have a colon then put the data type which is a standard 05:16.620 --> 05:25.110 logic vector with underscores between the standard logic and the logic and vector and then have 7 down 05:25.110 --> 05:32.850 to zero which indicates that we have 8 bits from 7 0 and colon equals the others. 05:32.850 --> 05:36.310 It was arrow and put one in parentheses. 05:36.510 --> 05:43.650 Well that's going to do is give us a signal a bit hyped and logic vector 8 bits wide and all the values 05:43.680 --> 05:53.040 will be equal to 1 and we're doing the same with the signal we're going to call red saw the score range. 05:53.100 --> 05:59.600 Now we have a red edge and we want to give the initial value of 0. 05:59.790 --> 06:06.420 So we're going to have to signal signal a signal a red a red is going to be the same exact size same 06:06.420 --> 06:10.640 data type standard logic vector over a red nose. 06:10.710 --> 06:11.760 It has a 1. 06:11.760 --> 06:14.130 We want to make it initial value of all zeroes. 06:14.130 --> 06:20.360 So I have to do is on the one backspace Weiss's zero in there. 06:20.400 --> 06:27.060 So now we have signal a of 8 bits all ones signal A-rag that's all zeros. 06:27.320 --> 06:30.620 And made a little note in here just to kind of show you this is correct. 06:30.990 --> 06:33.090 So I wanted to take. 06:33.110 --> 06:40.360 They make it equal to a red edge and or that I just type the arrow equals. 06:40.500 --> 06:43.290 So and this is a concurrent statement. 06:43.290 --> 06:50.070 So always were were saying that our signal a red edge is being kept the same way. 06:50.100 --> 06:58.550 A lot of times you'll do this when you have to not have two signals but when you have a signal but it's 06:58.660 --> 07:02.650 like of a with an output on the port map it has a red edge. 07:02.700 --> 07:05.150 So you can write values into this registry. 07:05.330 --> 07:08.320 And then the map too. 07:09.510 --> 07:18.600 So if you know after this point of her 1:42 our signal is equal to all zeros and way red equals it's 07:19.770 --> 07:26.660 quick little example showing you how to initialize values and HGL and give them some meaning.