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Well sign the initial values in VHDL.

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Are a few examples we can look at to show you how that is done.

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So first for line number one.

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Just a quick comment to showing you that in your dash dash your comment and your work you know notepad

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plus plus as you put the dash dash there you'll notice that your text or anything and type turns green.

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So it's pretty neat that when you type a key word and no Paphos Plus how is it what you know that it

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recognizes that it's a VHDL file.

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So we go ahead and type a type signal in here which is a key word and VHDL and you see this is this.

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As soon as I start to type it it shows up there in the dropdown I go and hit enter and then it turns

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blue and Kate knows that that's a signal.

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And so is the quick way to bet if you're using the Apply Plus plus a key thing to remember if you're

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editing a file in Notepad plus plus when you if you go to a file you go ahead and create a new file

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and it's going to right away.

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It is called a normal text file.

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Want to click on language go down to be like VHDL.

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Now it will call it the age as I see Hurlburt a script of mine which file.

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So now if I type it will pick up signal because I know that that's the key word enter.

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It makes it blude indicate that that's a key word.

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I'm not going to keep this almanacks of that.

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So I will go to our back to our example here.

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And so first I have signal A which is a type of integer and I want to give an initial value of 4.

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So I have my signal a then I have to do a semi-colon there to a colon to indicate that my data type

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which is in the keyword which you notice is is purple.

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And then I'll give it a colon equals four.

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So what this is doing is I'm saying I have a signal I'm calling it a.

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It has an integer type integer an initial value of.

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If we move down to three on line with a mindset and we have signal B and.

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And do you mean this is a type unsigned with an initial value of 0 0 0 0 because we work with unsigned

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and signed.

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We have to give it the actual bit values because an integer we can't give it like a 1 or 0 or so on

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and so forth.

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And so if you look I have signal B my colon indicates the data type unsigned and I give you the keywords

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3 down to zero which just means I have an unsigned data type of 4 bits and if you look then I have a

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colon equals which I'm going to have the double parentheses which just indicates all the bits.

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So it's giving an actually signal B is four bits.

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All of them are initialized to zero and B one if you look on line 10 is doing the exact same thing except

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we're using the other's key word message to show you you initialize with larger values that you can

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see that instead of if I would have liked this is only forbit.

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So it's not as big of an issue.

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But if this were to be I don't know like a 12 or 24 32 ribbon 64 bit signal instead of putting in 64

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zeros in my file.

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I can just have this other.

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And the zeros there and that keyword will actually initialize a signal be 4 bits wide all with zero.

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And if you look down on lines 18 21 with my signal C and C 1 we're doing the exact same thing except

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that we're working with these are actually signed values which I have as unsigned because OK I can just

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go ahead and read that down to see one on line 21 and move on.

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So now signal C and C 1 are doing the same thing as signal B and B one except there sign two types as

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opposed unsigned.

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And we initialize them in the same way we use the colon equals and give it the value y initialize it

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to move down.

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Let's look at signing initial values to standard logic sectors.

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So we have a signal looking on line 31 we wanted to fine signal a signal and name a as a standard logic

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vector data type with an initial value of all ones and count them not there but there's eight ones.

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So what we'll do.

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We want to put the key signal and type a and have a colon then put the data type which is a standard

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logic vector with underscores between the standard logic and the logic and vector and then have 7 down

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to zero which indicates that we have 8 bits from 7 0 and colon equals the others.

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It was arrow and put one in parentheses.

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Well that's going to do is give us a signal a bit hyped and logic vector 8 bits wide and all the values

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will be equal to 1 and we're doing the same with the signal we're going to call red saw the score range.

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Now we have a red edge and we want to give the initial value of 0.

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So we're going to have to signal signal a signal a red a red is going to be the same exact size same

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data type standard logic vector over a red nose.

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It has a 1.

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We want to make it initial value of all zeroes.

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So I have to do is on the one backspace Weiss's zero in there.

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So now we have signal a of 8 bits all ones signal A-rag that's all zeros.

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And made a little note in here just to kind of show you this is correct.

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So I wanted to take.

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They make it equal to a red edge and or that I just type the arrow equals.

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So and this is a concurrent statement.

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So always were were saying that our signal a red edge is being kept the same way.

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A lot of times you'll do this when you have to not have two signals but when you have a signal but it's

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like of a with an output on the port map it has a red edge.

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So you can write values into this registry.

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And then the map too.

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So if you know after this point of her 1:42 our signal is equal to all zeros and way red equals it's

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quick little example showing you how to initialize values and HGL and give them some meaning.