WEBVTT 00:12.430 --> 00:18.340 Look at the standard logic factors standard logic data types lecture in this lecture I'm going to explain 00:18.340 --> 00:27.700 to the HDL data types standard logics and standard logic vectors standard logic data types are defined 00:27.940 --> 00:35.010 and package standard logic 1 1 6 4 stair logic type is either a 1 or a zero. 00:35.060 --> 00:41.030 At this level is based upon the voltage level supplied to the FPGA. 00:41.540 --> 00:45.070 So to us we say sound or logic is a 1 or 0. 00:45.090 --> 00:51.120 But inside that APJ for parent with a three point three a logic one is a three point three ball and 00:51.120 --> 00:58.240 the logic 0 would be a zero goal or for powering it with 2.5 volts logic one will be 2.5 volts and zero 00:58.300 --> 00:59.650 would be zero. 00:59.800 --> 01:04.540 It's a standard logic to type as a single binary bit. 01:04.630 --> 01:11.090 And this is denoted by the keyword as Tity underscore L-O GC or standard logic. 01:12.510 --> 01:18.630 Let's take a look at a standard logic Stehr loving datatypes are commonly used as flags or indicators 01:18.950 --> 01:24.460 that either tell you a yes or no you're good to go you're not a lot of times these and to indicate a 01:24.480 --> 01:25.770 delay has been reached. 01:25.770 --> 01:29.400 A button has been pushed or other things of this nature. 01:29.760 --> 01:35.940 So if we have let's look at how do we do you know a standard logic we have or data class which is a 01:35.940 --> 01:43.140 signal or signal name which we're calling P.W. and underscore value in our data type we're specifying 01:43.140 --> 01:47.050 as a standard logic and we're giving it an initial value of zero. 01:47.130 --> 01:53.370 The only other option we can give it as a one if we try to put two zeros or two ones in their synthesizer 01:53.610 --> 01:55.440 is going to throw out an error at a time. 01:55.500 --> 01:56.400 This is an invalid error. 01:56.400 --> 01:59.840 I don't know what it can be either can be a one or a zero. 02:01.430 --> 02:08.840 Standard logic vector data types they are also defined in a package standard logic one 1:06 for a standard 02:08.840 --> 02:13.330 logic factor is a set of multiple standard logic values. 02:13.370 --> 02:18.770 So if you think of the name standard logic factor it's a vector of standard logics. 02:18.770 --> 02:26.510 So your standard logic is a single bit a standard logic vector is multiple bits and the wit or the number 02:26.510 --> 02:30.760 of bits you specify when you denote the standard logic vector. 02:31.250 --> 02:35.840 So with a a vector you can be any combinations of ones and zeros. 02:35.900 --> 02:44.360 If you have to let's say it's a two bit wit you can have it 0 0 1 0 1 1 or any any combination between 02:44.360 --> 02:53.030 you can come up with a standard logic vector as denoted by as to the underscore EHLO g i c underscore 02:53.090 --> 02:58.260 vector or standard logic vector an example. 02:58.310 --> 03:07.040 We use standard logic vector datatypes are commonly used to hold address's data Ltd. to light up LCD. 03:07.160 --> 03:11.840 You can use it to send data to a 7st display or a lot of different things. 03:11.840 --> 03:18.020 This is a very commonly used data type in the HDL and the main advantage is that you can individually 03:18.020 --> 03:19.300 toggle bits. 03:19.310 --> 03:25.730 So if you have for example a simple example a whole array of Ltds you can create a standard logic vector 03:25.730 --> 03:28.300 to a whit if you have 15 trollies. 03:28.460 --> 03:33.930 You make it 15 bits wide and you can individually toggle each bit to either turn that Elodie on or turn 03:33.930 --> 03:35.470 that Elodie off. 03:35.480 --> 03:42.330 So if we have an example of how do we create a center logic vector we have our data class which is a 03:42.330 --> 03:49.790 signal we have our single name we're calling seg out in our data type is the standard logic vector and 03:49.790 --> 03:53.310 then we specify the size of that standard logic factor. 03:53.390 --> 03:59.310 In this case we're specifying it to be 7 bits wide from 6 down to zero. 03:59.340 --> 04:01.290 That gives us a total of seven bits. 04:01.460 --> 04:04.960 And then our initial value is the actual value of those bits. 04:04.970 --> 04:13.390 So we have 1 0 1 0 0 0 and with that initial value that can be any combination of ones and zeros. 04:13.550 --> 04:15.250 We want to come up with. 04:16.550 --> 04:21.100 And that is a standard logic and Sandu logic data vectors lecture.