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Look at the standard logic factors standard logic data types lecture in this lecture I'm going to explain

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to the HDL data types standard logics and standard logic vectors standard logic data types are defined

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and package standard logic 1 1 6 4 stair logic type is either a 1 or a zero.

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At this level is based upon the voltage level supplied to the FPGA.

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So to us we say sound or logic is a 1 or 0.

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But inside that APJ for parent with a three point three a logic one is a three point three ball and

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the logic 0 would be a zero goal or for powering it with 2.5 volts logic one will be 2.5 volts and zero

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would be zero.

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It's a standard logic to type as a single binary bit.

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And this is denoted by the keyword as Tity underscore L-O GC or standard logic.

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Let's take a look at a standard logic Stehr loving datatypes are commonly used as flags or indicators

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that either tell you a yes or no you're good to go you're not a lot of times these and to indicate a

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delay has been reached.

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A button has been pushed or other things of this nature.

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So if we have let's look at how do we do you know a standard logic we have or data class which is a

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signal or signal name which we're calling P.W. and underscore value in our data type we're specifying

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as a standard logic and we're giving it an initial value of zero.

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The only other option we can give it as a one if we try to put two zeros or two ones in their synthesizer

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is going to throw out an error at a time.

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This is an invalid error.

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I don't know what it can be either can be a one or a zero.

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Standard logic vector data types they are also defined in a package standard logic one 1:06 for a standard

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logic factor is a set of multiple standard logic values.

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So if you think of the name standard logic factor it's a vector of standard logics.

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So your standard logic is a single bit a standard logic vector is multiple bits and the wit or the number

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of bits you specify when you denote the standard logic vector.

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So with a a vector you can be any combinations of ones and zeros.

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If you have to let's say it's a two bit wit you can have it 0 0 1 0 1 1 or any any combination between

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you can come up with a standard logic vector as denoted by as to the underscore EHLO g i c underscore

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vector or standard logic vector an example.

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We use standard logic vector datatypes are commonly used to hold address's data Ltd. to light up LCD.

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You can use it to send data to a 7st display or a lot of different things.

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This is a very commonly used data type in the HDL and the main advantage is that you can individually

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toggle bits.

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So if you have for example a simple example a whole array of Ltds you can create a standard logic vector

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to a whit if you have 15 trollies.

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You make it 15 bits wide and you can individually toggle each bit to either turn that Elodie on or turn

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that Elodie off.

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So if we have an example of how do we create a center logic vector we have our data class which is a

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signal we have our single name we're calling seg out in our data type is the standard logic vector and

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then we specify the size of that standard logic factor.

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In this case we're specifying it to be 7 bits wide from 6 down to zero.

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That gives us a total of seven bits.

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And then our initial value is the actual value of those bits.

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So we have 1 0 1 0 0 0 and with that initial value that can be any combination of ones and zeros.

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We want to come up with.

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And that is a standard logic and Sandu logic data vectors lecture.