WEBVTT 00:12.850 --> 00:19.540 Walk to the introduction to VHDL in this lecture I'm going to introduce and explain the HDL and what 00:19.540 --> 00:23.090 it is use for fish. 00:23.340 --> 00:32.920 This stands for the h s I see hardware descriptive language and VHS I see stands for very high speed 00:33.190 --> 00:35.020 integrated circuit. 00:35.020 --> 00:40.450 And what my HDL is used for is to describe the actual physical circuit and that's exactly what we're 00:40.450 --> 00:47.560 doing with the HGL we are describing a circuit using code or VHDL to physically describe how we want 00:47.560 --> 00:51.740 that digital circuit to operate. 00:51.740 --> 00:58.960 Let's just talk a little bit about the history HDL VHDL was developed in 1981 by the Department of Defense 00:59.560 --> 01:05.470 and the reason they created the HDL was they develop this as a way to address the hardware lifecycle 01:05.470 --> 01:07.600 crisis of electronic systems. 01:07.690 --> 01:14.610 If you have a circuit board with a lot of integrated circuits and with electronic systems and Atrox 01:14.650 --> 01:20.520 today we know that every so many years that here the current components are using go out of date. 01:20.530 --> 01:25.570 They have newer the latest and greatest in the Department of Defense wants the latest integrated technology. 01:25.570 --> 01:32.680 However it becomes very task for very hard to re engineer or relay out a board. 01:32.680 --> 01:40.390 So the VHDL is used as a way to replace that you can put an FPGA a C PLB on your circuit board. 01:40.390 --> 01:46.540 And so as standards change and electronics evolve you can implement a new program to run on there and 01:46.540 --> 01:48.050 kind of mitigate that risk. 01:48.430 --> 01:55.360 And the department offense gave away all rights of the language to the Tripoli the Institute of Electrical 01:55.630 --> 01:57.050 and Electronics Engineers. 01:57.190 --> 02:01.910 And so they're the ones that are in charge of the VHDL language defining the standards. 02:01.960 --> 02:03.560 So on and so forth. 02:05.080 --> 02:14.350 Different devices that use VHDL are one is PJ's which are field programmable get arrays and this class 02:14.350 --> 02:19.480 that's what we'll be using with our different villain boards will be having an FPGA on there that we're 02:19.480 --> 02:25.510 going to be writing the HDL code to describe the circuits that will be operating on these FPGA. 02:25.950 --> 02:30.580 Then you had a CPA L.D. which is a complex programmable logic device. 02:30.580 --> 02:37.990 These are in a way you can think of them as a smaller more less capable FPGA and FPGA is a lot more 02:37.990 --> 02:38.690 powerful. 02:38.740 --> 02:47.090 A CPO is less powerful then we have a sick which is an application specific integrated circuit. 02:47.140 --> 02:56.540 This would be anything like if you have a shift register built into an icy chip or a processor microprocessor. 02:56.650 --> 02:58.460 All these are considered basic. 02:58.480 --> 03:05.680 This is a chip that has a specific designated function and you can use VHDL to write how you want the 03:05.680 --> 03:07.430 circuit inside of it to work. 03:07.570 --> 03:12.400 And then there's different tools you can use to take your VHDL and turn it into transistors and gates 03:12.520 --> 03:16.280 and implement it actually on the physical silicone. 03:17.500 --> 03:20.120 So we're talking at PJ's Or C A. 03:20.260 --> 03:25.660 Let's do a little comparison between the two Apogees their design using logic blocks. 03:25.750 --> 03:29.600 They have a much higher logic capacity than a CPD. 03:29.800 --> 03:35.620 And typically we use an FPGA for a much more complex or high bandwidth designs. 03:35.650 --> 03:37.280 They have multiple memory. 03:37.330 --> 03:40.530 When you power off the FPGA loses its configuration. 03:40.540 --> 03:45.820 So every time you kind of power back on your FPGA has to read in the configuration file whether it be 03:45.820 --> 03:52.420 from J tag or in on chip flash or an SD card or whatever type of memory device that's going to load 03:52.540 --> 03:58.690 the configuration file into that Pejic and typically beings that FPGA is more powerful and more capable 03:58.960 --> 04:05.910 they are more expensive and Sebille these now CPB may have less capacity than FPGA. 04:06.010 --> 04:09.920 They are typically used when you have a simpler less complex design. 04:10.300 --> 04:15.760 However they do have nonvolatile memory meaning if you turn the CPV off and turn the power back on the 04:15.780 --> 04:20.650 Sebille the remains that configuration of ice so you don't have to have an external memory device. 04:20.770 --> 04:25.800 All of that TPL d to load back in every time you turn the power back on. 04:26.140 --> 04:28.750 And typically they're are more cost effective than apogee. 04:28.870 --> 04:33.040 And you have a very simple basic design and you can fit it on a. 04:33.360 --> 04:34.900 You are more apt to do that. 04:34.900 --> 04:40.250 However if you think in the future your design is going to grow or you want to add more to that your 04:40.310 --> 04:41.000 going to go. 04:41.090 --> 04:50.470 PJ It's a lot more powerful and to major manufacturers of FPGA and speel these are Xilinx and Altera 04:52.880 --> 04:54.150 some key points. 04:54.250 --> 04:57.630 The HTL is not a programming language. 04:57.700 --> 04:59.340 We're not actually programming. 04:59.350 --> 05:05.890 PJ we're writing a configuration file or writing or describing how we want an actual physical digital 05:05.890 --> 05:08.800 circuit to run on the FPGA. 05:09.580 --> 05:15.950 And along with the same point VHDL is software it is used to describe the hardware the software would 05:15.950 --> 05:16.550 run on. 05:16.700 --> 05:22.340 So if you have a processor you would write VHDL to describe that processor and then you could write 05:22.340 --> 05:30.020 software that would run on the processor where the actual synthesize the compiler runs to the code and 05:30.020 --> 05:36.320 constructs the gate specified in the VHDL code and it limits them on the target logic device and the 05:36.320 --> 05:41.300 top two manufacturers at and CPM these or Xilinx and Altera 05:44.040 --> 05:45.540 that is VHDL to a high level. 05:45.540 --> 05:47.820 Now let's get started getting into the details.