1 00:00:12,850 --> 00:00:19,540 Walk to the introduction to VHDL in this lecture I'm going to introduce and explain the HDL and what 2 00:00:19,540 --> 00:00:23,090 it is use for fish. 3 00:00:23,340 --> 00:00:32,920 This stands for the h s I see hardware descriptive language and VHS I see stands for very high speed 4 00:00:33,190 --> 00:00:35,020 integrated circuit. 5 00:00:35,020 --> 00:00:40,450 And what my HDL is used for is to describe the actual physical circuit and that's exactly what we're 6 00:00:40,450 --> 00:00:47,560 doing with the HGL we are describing a circuit using code or VHDL to physically describe how we want 7 00:00:47,560 --> 00:00:51,740 that digital circuit to operate. 8 00:00:51,740 --> 00:00:58,960 Let's just talk a little bit about the history HDL VHDL was developed in 1981 by the Department of Defense 9 00:00:59,560 --> 00:01:05,470 and the reason they created the HDL was they develop this as a way to address the hardware lifecycle 10 00:01:05,470 --> 00:01:07,600 crisis of electronic systems. 11 00:01:07,690 --> 00:01:14,610 If you have a circuit board with a lot of integrated circuits and with electronic systems and Atrox 12 00:01:14,650 --> 00:01:20,520 today we know that every so many years that here the current components are using go out of date. 13 00:01:20,530 --> 00:01:25,570 They have newer the latest and greatest in the Department of Defense wants the latest integrated technology. 14 00:01:25,570 --> 00:01:32,680 However it becomes very task for very hard to re engineer or relay out a board. 15 00:01:32,680 --> 00:01:40,390 So the VHDL is used as a way to replace that you can put an FPGA a C PLB on your circuit board. 16 00:01:40,390 --> 00:01:46,540 And so as standards change and electronics evolve you can implement a new program to run on there and 17 00:01:46,540 --> 00:01:48,050 kind of mitigate that risk. 18 00:01:48,430 --> 00:01:55,360 And the department offense gave away all rights of the language to the Tripoli the Institute of Electrical 19 00:01:55,630 --> 00:01:57,050 and Electronics Engineers. 20 00:01:57,190 --> 00:02:01,910 And so they're the ones that are in charge of the VHDL language defining the standards. 21 00:02:01,960 --> 00:02:03,560 So on and so forth. 22 00:02:05,080 --> 00:02:14,350 Different devices that use VHDL are one is PJ's which are field programmable get arrays and this class 23 00:02:14,350 --> 00:02:19,480 that's what we'll be using with our different villain boards will be having an FPGA on there that we're 24 00:02:19,480 --> 00:02:25,510 going to be writing the HDL code to describe the circuits that will be operating on these FPGA. 25 00:02:25,950 --> 00:02:30,580 Then you had a CPA L.D. which is a complex programmable logic device. 26 00:02:30,580 --> 00:02:37,990 These are in a way you can think of them as a smaller more less capable FPGA and FPGA is a lot more 27 00:02:37,990 --> 00:02:38,690 powerful. 28 00:02:38,740 --> 00:02:47,090 A CPO is less powerful then we have a sick which is an application specific integrated circuit. 29 00:02:47,140 --> 00:02:56,540 This would be anything like if you have a shift register built into an icy chip or a processor microprocessor. 30 00:02:56,650 --> 00:02:58,460 All these are considered basic. 31 00:02:58,480 --> 00:03:05,680 This is a chip that has a specific designated function and you can use VHDL to write how you want the 32 00:03:05,680 --> 00:03:07,430 circuit inside of it to work. 33 00:03:07,570 --> 00:03:12,400 And then there's different tools you can use to take your VHDL and turn it into transistors and gates 34 00:03:12,520 --> 00:03:16,280 and implement it actually on the physical silicone. 35 00:03:17,500 --> 00:03:20,120 So we're talking at PJ's Or C A. 36 00:03:20,260 --> 00:03:25,660 Let's do a little comparison between the two Apogees their design using logic blocks. 37 00:03:25,750 --> 00:03:29,600 They have a much higher logic capacity than a CPD. 38 00:03:29,800 --> 00:03:35,620 And typically we use an FPGA for a much more complex or high bandwidth designs. 39 00:03:35,650 --> 00:03:37,280 They have multiple memory. 40 00:03:37,330 --> 00:03:40,530 When you power off the FPGA loses its configuration. 41 00:03:40,540 --> 00:03:45,820 So every time you kind of power back on your FPGA has to read in the configuration file whether it be 42 00:03:45,820 --> 00:03:52,420 from J tag or in on chip flash or an SD card or whatever type of memory device that's going to load 43 00:03:52,540 --> 00:03:58,690 the configuration file into that Pejic and typically beings that FPGA is more powerful and more capable 44 00:03:58,960 --> 00:04:05,910 they are more expensive and Sebille these now CPB may have less capacity than FPGA. 45 00:04:06,010 --> 00:04:09,920 They are typically used when you have a simpler less complex design. 46 00:04:10,300 --> 00:04:15,760 However they do have nonvolatile memory meaning if you turn the CPV off and turn the power back on the 47 00:04:15,780 --> 00:04:20,650 Sebille the remains that configuration of ice so you don't have to have an external memory device. 48 00:04:20,770 --> 00:04:25,800 All of that TPL d to load back in every time you turn the power back on. 49 00:04:26,140 --> 00:04:28,750 And typically they're are more cost effective than apogee. 50 00:04:28,870 --> 00:04:33,040 And you have a very simple basic design and you can fit it on a. 51 00:04:33,360 --> 00:04:34,900 You are more apt to do that. 52 00:04:34,900 --> 00:04:40,250 However if you think in the future your design is going to grow or you want to add more to that your 53 00:04:40,310 --> 00:04:41,000 going to go. 54 00:04:41,090 --> 00:04:50,470 PJ It's a lot more powerful and to major manufacturers of FPGA and speel these are Xilinx and Altera 55 00:04:52,880 --> 00:04:54,150 some key points. 56 00:04:54,250 --> 00:04:57,630 The HTL is not a programming language. 57 00:04:57,700 --> 00:04:59,340 We're not actually programming. 58 00:04:59,350 --> 00:05:05,890 PJ we're writing a configuration file or writing or describing how we want an actual physical digital 59 00:05:05,890 --> 00:05:08,800 circuit to run on the FPGA. 60 00:05:09,580 --> 00:05:15,950 And along with the same point VHDL is software it is used to describe the hardware the software would 61 00:05:15,950 --> 00:05:16,550 run on. 62 00:05:16,700 --> 00:05:22,340 So if you have a processor you would write VHDL to describe that processor and then you could write 63 00:05:22,340 --> 00:05:30,020 software that would run on the processor where the actual synthesize the compiler runs to the code and 64 00:05:30,020 --> 00:05:36,320 constructs the gate specified in the VHDL code and it limits them on the target logic device and the 65 00:05:36,320 --> 00:05:41,300 top two manufacturers at and CPM these or Xilinx and Altera 66 00:05:44,040 --> 00:05:45,540 that is VHDL to a high level. 67 00:05:45,540 --> 00:05:47,820 Now let's get started getting into the details.