WEBVTT 00:12.650 --> 00:18.710 Welcome to the course in this lecture I'm going to introduce myself the course layout and what to expect 00:18.800 --> 00:21.300 from this course about me. 00:21.380 --> 00:27.230 I have a master's of science and electrical engineering with a focus on embedded systems. 00:27.230 --> 00:34.100 I'm currently working as an engineer where I work on firmware pokus on the processors the CPO DS and 00:34.100 --> 00:36.140 microprocessors. 00:36.170 --> 00:41.630 I absolutely love working with electronics especially embedded systems for all those fellow fliers out 00:41.630 --> 00:42.050 there. 00:42.050 --> 00:49.550 Go Eudy the course deliverables upon completion this course you should be able to do the following. 00:49.560 --> 00:56.000 I want you to be able to read and understand a VHDL design as well as create your own VHDL design. 00:56.250 --> 01:01.560 I want you to take your own ideas and have the tools to be able to say OK I had this idea I want to 01:01.560 --> 01:05.800 implement it on PGA using VHDL. 01:05.910 --> 01:11.490 And so you have the tools to be able to do that and also program an FPGA development board. 01:11.580 --> 01:18.360 If someone gives you a set of VHDL design files I want you to know how to take those Impalas create 01:18.360 --> 01:27.570 a configuration file and load it on the FPGA as well as take a configuration file and program the FPGA. 01:27.570 --> 01:31.700 The way this course is laid out is that they are the first several sections. 01:31.740 --> 01:39.510 I discussed the specifics of the VHDL language we talk about the data types the different coding structures 01:39.600 --> 01:40.810 and the styles. 01:40.920 --> 01:45.320 We also discuss the tools provided by Xilinx and Altera. 01:45.480 --> 01:47.710 These are the major players in the FPGA. 01:47.750 --> 01:49.340 See PLB world. 01:49.350 --> 01:53.460 Then after that we go through and complete a set of seven labs. 01:53.460 --> 01:58.540 These labs vary from a basic adder to a more complex RC servo controller. 01:58.770 --> 02:04.620 And for each of these labs I have a set of my HDL design files to start from. 02:04.710 --> 02:10.190 You will take these files and have to modify them to fit to actually get the lab to do what we want 02:10.260 --> 02:10.850 it to. 02:10.860 --> 02:15.930 But upon completing this course you'll have all these complete labs and a set of design files to work 02:15.930 --> 02:17.740 from in the future. 02:18.450 --> 02:24.840 If you find yourself not being challenged by this course I have a set of more challenging courses that 02:24.930 --> 02:26.540 FPGA turbo series. 02:26.640 --> 02:27.680 I have several of them. 02:27.680 --> 02:34.950 They include implementing a you are or we go through and I explain the protocol and the design steps 02:34.950 --> 02:36.990 required to implement this. 02:36.990 --> 02:39.410 You are inside of your FPGA. 02:39.450 --> 02:44.460 And so I also give you files to start from where you will complete them and upon completing this you 02:44.460 --> 02:51.030 will have a fully functional you are that you can type commands in your computer to make specific things 02:51.030 --> 02:52.570 happen on your PGA. 02:52.890 --> 02:59.040 We also had a communication protocols course where we go through various communication protocols used 02:59.400 --> 03:02.750 in the industry that we implement on the FPGA. 03:02.760 --> 03:08.580 And one of these protocols is an infrared receiver will actually be able to read the infrared rays coming 03:08.940 --> 03:16.120 from a TV standard TV remote and be able to implement them and understand what is going on and find 03:16.120 --> 03:21.930 one we have is the advanced LCD control course where we will go through and I'll show you how to vary 03:21.930 --> 03:28.290 the brightness of an LCD make a certain melodies change color as well as a string of neo picks well 03:28.290 --> 03:33.330 IDs to individually change the color on every one of those. 03:33.570 --> 03:36.680 Enough talking about me let's get started learning about VHDL.