RC_servo Project Status
Project File: RC_servo.xise Parser Errors: No Errors
Module Name: RC_servo Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 90 1,920 4%  
Number of 4 input LUTs 56 1,920 2%  
Number of occupied Slices 73 960 7%  
    Number of Slices containing only related logic 73 73 100%  
    Number of Slices containing unrelated logic 0 73 0%  
Total Number of 4 input LUTs 132 1,920 6%  
    Number used as logic 56      
    Number used as a route-thru 76      
Number of bonded IOBs 17 83 20%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Jul 30 22:37:49 201501 Warning (0 new)2 Infos (0 new)
Translation ReportCurrentThu Jul 30 22:37:55 2015000
Map ReportCurrentThu Jul 30 22:37:59 2015002 Infos (0 new)
Place and Route ReportCurrentThu Jul 30 22:38:11 2015004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Jul 30 22:38:13 2015005 Infos (0 new)
Bitgen ReportCurrentThu Jul 30 22:38:36 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Jul 30 22:38:36 2015
WebTalk Log FileCurrentThu Jul 30 22:38:42 2015

Date Generated: 12/18/2015 - 20:42:24