1 00:00:01,230 --> 00:00:03,780 Welcome to lab 6 the multiplier 2 00:00:05,970 --> 00:00:13,380 multiplication in FPGA is FPGA is by nature are not designed to implement multiplication. 3 00:00:13,380 --> 00:00:18,360 However most FPGA today have embedded dedicated multipliers. 4 00:00:18,360 --> 00:00:25,980 The Spartan 3 which is the FPGA we are using contains only four dedicated multipliers. 5 00:00:26,130 --> 00:00:33,890 So if all these are being used by different process we would have to implement one of our own binary 6 00:00:33,910 --> 00:00:37,540 multiplication in order to implement our multiplier. 7 00:00:37,570 --> 00:00:41,720 We will be simulating binary multiplication of two numbers. 8 00:00:41,740 --> 00:00:49,660 Here is an example of binary 12 in binary 13 multiplied which produces the same result as a decimal 9 00:00:49,660 --> 00:00:50,710 equivalent. 10 00:00:50,710 --> 00:00:56,950 This process just takes more time to complete multiplier state machine. 11 00:00:57,020 --> 00:01:03,800 We will be implementing a state machine to determine when we are shifting adding and when the multiplication 12 00:01:03,800 --> 00:01:04,780 is done. 13 00:01:04,880 --> 00:01:09,930 Take note of the names of the different state machines and the signal names. 14 00:01:09,950 --> 00:01:16,680 When you look at the VHDL design file multipliers state diagram. 15 00:01:16,900 --> 00:01:20,930 Here is a block diagram solution to the multiplier design lab. 16 00:01:20,960 --> 00:01:24,620 Note the name values when you're looking at the multiplier. 17 00:01:24,620 --> 00:01:29,650 VHDL design file multiplier operation. 18 00:01:29,790 --> 00:01:37,450 Here's a table to give you a much more clear understanding of what is going on inside the multiplier. 19 00:01:37,450 --> 00:01:44,140 We will be creating a force multiplier so that way we can implement this design on the basis to board. 20 00:01:44,350 --> 00:01:49,470 However this design can be scaled up or down to whatever size you would like. 21 00:01:50,870 --> 00:01:53,010 Mollison simulation. 22 00:01:53,060 --> 00:01:59,460 Here's a screenshot showing the multiplier simulation. 23 00:02:00,000 --> 00:02:02,700 Here are the tasks for lab 6. 24 00:02:02,700 --> 00:02:12,810 Complete the molt 1 HD design utilizing the state machine simulate your completed design and model asem 25 00:02:13,770 --> 00:02:20,110 implement your completed design using Xilinx IAC and run it on your bases to board. 26 00:02:20,110 --> 00:02:27,890 No you will have to modify the file using the U.S.A file. 27 00:02:27,900 --> 00:02:32,970 I have given to you here the locations of the different entity port members. 28 00:02:32,970 --> 00:02:40,770 Feel free to modify the VHDL code see if you can display the result on the 7 segment displays by instantiating 29 00:02:41,040 --> 00:02:46,750 the hex to 7 seg component using lab 4 as an example. 30 00:02:47,340 --> 00:02:51,250 Upon the completion of lab 6 Here are the outcomes. 31 00:02:51,360 --> 00:02:58,200 You understand how a state machine can be used and implemented become more comfortable with FPGA prototyping 32 00:02:58,800 --> 00:03:02,790 understand how to add a user constraints file on an FPGA.