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Welcome to Lab 5 counter

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Moulson simulation here is the model some output of the counter.

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If you change the rate x to unsigned it is easier to read refer to all Taro's tools section Mollison

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video.

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If you're unsure how to do this.

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Here are the tasks for Lab 5.

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Modify counter 1.

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VHDL file to create a counter that counts from 0 to 255.

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I suggest implementing processes to achieve this successfully simulate this design and model some into

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what this design on your base is to board.

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You see if pin mapping using the U.S.A file I have given you here the locations of all the different

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entity port members you should see a counter accounts from 0 to 255 and binary on the Ltds when you

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press the reset button which is button zero.

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You should see the count start back at 0.

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Here are the outcomes.

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Upon completion of Lab 5 you should understand the use of the generate statement.

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Learn how to design and develop processes in your VHDL design.

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Understand how useful counters are and what they can be used for.