WEBVTT 00:00.980 --> 00:10.440 In a lab for hack's to seven segment display 7 segment display the Base to board contains four seven 00:10.440 --> 00:11.790 segment displays. 00:11.940 --> 00:18.120 We will be using two of them for this assignment seven segment displays are useful for conveying data 00:18.570 --> 00:20.630 easily for humans to read. 00:20.730 --> 00:27.840 We will be using the two displays to represent a single byte which is 8 bits of data which is represented 00:28.170 --> 00:34.700 by the switches on the bases two board bases two board user guide. 00:34.710 --> 00:41.270 Here are some images I pulled from the bases to user guide the 7 segment displays on the base is to 00:41.280 --> 00:48.600 board or comany and this means that the anode or negative sides of the Pleiades are connected to each 00:48.600 --> 00:54.680 other in order to light up a segment we need to drive a logic zero on the output. 00:54.750 --> 00:57.480 Also know that the displays are tied together. 00:57.480 --> 01:01.750 So we need to multiplex the outputs of the display. 01:01.750 --> 01:07.180 Another thing to look at is that we are using the N.P. transistors to drive the display. 01:07.380 --> 01:14.540 So you need a logic zero to allow current to flow through Moulson simulation. 01:14.550 --> 01:17.910 Note that we are only simulating the Hexa servants. 01:18.270 --> 01:29.490 VHDL file the top level VHDL file lab for the HD will not need to be simulated Here's a tasking for 01:29.490 --> 01:37.860 lab for modify and simulate the Hexis 7 SAG VHI the file in Moulson to verify it is working correctly 01:38.460 --> 01:48.900 modify the lab for VHDL file to create two component instantiations implement the lab for BHB design 01:48.960 --> 01:52.140 onto the basis to board. 01:52.230 --> 02:00.720 You see if happening using the U.S. file I have given to you here are the locations of all the different 02:00.720 --> 02:04.010 entity port numbers. 02:04.220 --> 02:06.430 You've just completed lap 4. 02:06.560 --> 02:08.840 Here are the outcomes I understand. 02:08.880 --> 02:16.580 Hi multiplexers circuit works these VHDL processes to create a counter that will slow the 50 megahertz 02:16.580 --> 02:17.960 clock down. 02:17.960 --> 02:24.640 This is important to multiplex the 7st display become more familiar with the Xilinx IAC toolset.