1 00:00:00,840 --> 00:00:08,680 Welcomed a lab to the shift register shift register and map to. 2 00:00:08,740 --> 00:00:11,710 We will be creating a shift register. 3 00:00:11,710 --> 00:00:19,480 There are many types of shift registers parallel and parallel out Universal shift register serial and 4 00:00:19,600 --> 00:00:28,180 serial out serial in parallel and many others shift registers are a very integral part of any digital 5 00:00:28,180 --> 00:00:29,540 logic circuit. 6 00:00:29,590 --> 00:00:38,170 We will be creating a serial and serial out shift register in this lab model simulation. 7 00:00:38,370 --> 00:00:42,940 Here's a screenshot of what your model sim simulation should look like. 8 00:00:42,940 --> 00:00:48,180 Note that there is no transcript output telling you that your simulation worked. 9 00:00:48,200 --> 00:00:52,220 There you can look at the wave form and see how the values are stepping down. 10 00:00:52,240 --> 00:01:00,580 Every clock cycle this is showing how big it is shifted through the register tasks complete the following 11 00:01:00,580 --> 00:01:01,360 tasks. 12 00:01:01,360 --> 00:01:10,900 For lab number to complete the shift edge VHDL design file I have given you successfully simulate your 13 00:01:10,900 --> 00:01:19,620 VHDL design using models and use modules 7.1 as a reference implement the completed shift register onto 14 00:01:19,630 --> 00:01:25,990 your bases to board using modules 8.2 8.3 as references. 15 00:01:26,920 --> 00:01:31,060 You C-f pin mapping using the use File. 16 00:01:31,060 --> 00:01:32,420 I have given you. 17 00:01:32,530 --> 00:01:36,760 Here are the locations of all the different entity port members. 18 00:01:36,760 --> 00:01:42,170 Feel free to modify the USCF file if you want to change the locations of things. 19 00:01:42,250 --> 00:01:46,680 I suggest you try and shift the outputs to left by for Ltds. 20 00:01:46,720 --> 00:01:51,510 This would be great practice and learning how to modify a U.S.A file. 21 00:01:52,240 --> 00:01:56,680 Here's a list of the outcomes upon the completion of lab to you. 22 00:01:56,680 --> 00:02:04,510 Again experience in coding VHDL you understand how a shift register works and is implemented in a VHDL 23 00:02:04,510 --> 00:02:05,530 design. 24 00:02:05,530 --> 00:02:09,220 Become more familiar with interpreting Madison simulations. 25 00:02:09,790 --> 00:02:16,750 Become more familiar with Xilinx IAC as a tool for creating programming files from a VHDL design.