1 00:00:00,840 --> 00:00:01,590 Hello everyone. 2 00:00:01,590 --> 00:00:04,150 Welcome to the lab one solutions. 3 00:00:04,200 --> 00:00:09,410 In this video I'm going to show you all the steps needed to complete lab one. 4 00:00:09,420 --> 00:00:13,310 So if you're ready let's get started here for lab one. 5 00:00:13,320 --> 00:00:13,900 I have. 6 00:00:14,000 --> 00:00:17,660 There is a zip file you need to download which is right here on my desktop. 7 00:00:18,030 --> 00:00:25,020 And so if you go ahead download that and extract it you'll see here's all the contents inside the lab 8 00:00:25,020 --> 00:00:26,250 one folder. 9 00:00:26,250 --> 00:00:34,400 I've got a folder underscore to a file which is used to the Mollison simulation. 10 00:00:34,410 --> 00:00:43,530 I've got a file which we use in the Xilinx ISC project and this water to it is the VHDL the actual design 11 00:00:43,530 --> 00:00:44,210 file. 12 00:00:44,460 --> 00:00:50,340 So if you right click on that I downloaded notepad plus plus you don't have to use it but just want 13 00:00:50,340 --> 00:00:55,880 to suggest ahead and open that up and you'll see this is the actual VHDL file I provided. 14 00:00:55,900 --> 00:01:02,640 You know notice this is a completed file there is no I don't. 15 00:01:02,640 --> 00:01:08,460 All I'm having to do with this here is just to run through the steps in creating a model sim simulation 16 00:01:09,030 --> 00:01:10,850 in a I.R.S. project. 17 00:01:10,890 --> 00:01:15,590 So there you will have to do any code editing for this lab. 18 00:01:15,600 --> 00:01:19,870 So OK we'll go ahead and normalize out of that now 19 00:01:22,850 --> 00:01:29,510 well I guess we have the lab one tasks which if I open up here gives you a list of all the tasks we 20 00:01:29,510 --> 00:01:36,860 need we need to complete for LAB 1 which are creating models project using the video as a reference 21 00:01:36,920 --> 00:01:45,230 and successfully simulate for our creative project and Xilinx IAC and to create a bit file which is 22 00:01:45,230 --> 00:01:52,060 what we use to program bases to board and then actually use that file to program the Base to board. 23 00:01:52,400 --> 00:01:52,870 OK. 24 00:01:52,940 --> 00:01:55,400 So here. 25 00:01:55,610 --> 00:01:56,210 Go ahead. 26 00:01:56,220 --> 00:01:58,350 No. 27 00:01:58,630 --> 00:02:05,320 So the first step will go ahead and open up our model Semb which if you open it up you should see something 28 00:02:05,380 --> 00:02:07,880 similar to this as your screen here. 29 00:02:08,170 --> 00:02:15,610 And the first step we need to do is change the directory to locate to the lab one folder we set which 30 00:02:15,610 --> 00:02:20,230 is look at our desktop head and all navigate to that 31 00:02:26,100 --> 00:02:33,730 and there it is OK and you have this little transcript down here running kind of telling you everything 32 00:02:33,730 --> 00:02:34,440 that's going on. 33 00:02:34,450 --> 00:02:40,240 So then the next step is we need to create a library for models and then any time you work in model 34 00:02:40,240 --> 00:02:46,690 assume you have to navigate to that directory and create a library to work out of so so a file new library 35 00:02:47,500 --> 00:02:55,900 and makes you select Create a new library in a logical mapping to it and the name Madison gives it his 36 00:02:55,900 --> 00:02:58,700 work and which is fine that's just the default name. 37 00:02:58,720 --> 00:03:00,050 That's the one I always use. 38 00:03:00,070 --> 00:03:01,970 Just go ahead and click OK. 39 00:03:02,040 --> 00:03:06,430 See the transcript telling you that it all is working fine. 40 00:03:06,430 --> 00:03:11,320 So now we want to do is go to Tools. 41 00:03:11,590 --> 00:03:18,520 This TCO execute macro and it brings us to our directory which is in the lab 1. 42 00:03:18,720 --> 00:03:25,700 It shows up you can select D.O. or a DCL file and I've provided you with the TCN file. 43 00:03:25,710 --> 00:03:27,260 Go ahead select that. 44 00:03:27,310 --> 00:03:34,300 This will run through and simulate your pulls in your testbench pulls in the design file and will create 45 00:03:34,300 --> 00:03:38,990 a simulation as you can see here on your screen. 46 00:03:39,430 --> 00:03:45,850 If you go through this is the full simulation and if you noticed down here the transcript window that 47 00:03:46,030 --> 00:03:51,580 gives you a note saying successful water tests completed which is good because I've given you the completed 48 00:03:51,930 --> 00:03:54,600 letter C shouldn't have to do any editing. 49 00:03:54,670 --> 00:03:57,900 And here in this wave window I'll go ahead. 50 00:03:58,030 --> 00:04:05,710 Right click and select on the Zoom for it all matches so it fits your window and you can see if I expand 51 00:04:05,710 --> 00:04:06,760 this here. 52 00:04:07,030 --> 00:04:15,290 It gives you all of the different signals we have in our entity or ASCI out x y S.N. and tell it shows 53 00:04:15,290 --> 00:04:19,490 and toggling your sense or logic tells you there is 0 or 1. 54 00:04:19,990 --> 00:04:26,300 And these are the signals we have in their test inputs and our test outputs. 55 00:04:26,410 --> 00:04:32,820 So that is right there we just completed task 1 which are successful models and simulation. 56 00:04:32,830 --> 00:04:36,450 So go ahead and close out of that. 57 00:04:36,850 --> 00:04:41,960 And the next thing we want to do is open up the ISC project. 58 00:04:41,980 --> 00:04:49,480 Now I'm using twelve point four which if you go to the download you can download fourteen point seven 59 00:04:49,690 --> 00:04:54,650 or any anything later than 2.4 should work. 60 00:04:54,670 --> 00:05:03,400 So go ahead and more click select new project bring up our new project wizard and we want to go ahead 61 00:05:03,400 --> 00:05:11,800 and navigate to the lab one folder that I zip file gave you that you extracted and we'll select that 62 00:05:11,830 --> 00:05:16,150 as our location for our new project. 63 00:05:16,160 --> 00:05:21,850 And as far as the name goes you want to give it the same name as the entity declaration or the VHDL 64 00:05:21,850 --> 00:05:22,910 file I gave you. 65 00:05:23,110 --> 00:05:28,610 And so that is full adder too. 66 00:05:29,080 --> 00:05:30,640 And you see this as a working directory. 67 00:05:30,640 --> 00:05:31,920 This is the location of it. 68 00:05:32,290 --> 00:05:39,770 And for your top level source you want to select HDL your hardware descriptive language and click next. 69 00:05:39,980 --> 00:05:41,710 And here is where you select. 70 00:05:41,740 --> 00:05:46,240 This is all the project settings where you basically specify the device you're targeting. 71 00:05:46,240 --> 00:05:49,280 So far our family is a Spartan 3. 72 00:05:49,330 --> 00:05:53,100 This is the FPGA that's located on the bases to board. 73 00:05:53,110 --> 00:05:59,830 If you're using a different board you'll want to select whichever family of FPGA your board your board 74 00:05:59,830 --> 00:06:01,680 has which it should be. 75 00:06:01,900 --> 00:06:06,820 Tell you in the documentation or user guide and the device is the X. 76 00:06:06,850 --> 00:06:08,960 See 3 x 100. 77 00:06:09,430 --> 00:06:18,520 Which is the one we're using on the basis to board and the ACP 132 pin package speed dash for synthesis 78 00:06:18,520 --> 00:06:26,160 tool will select the X s t and simulator I ice for language VHDL. 79 00:06:26,170 --> 00:06:28,720 Most all these here should be the defaults. 80 00:06:28,810 --> 00:06:34,320 However not just make sure what's on your screen matches what I have going on right here. 81 00:06:34,350 --> 00:06:34,890 You go ahead. 82 00:06:34,930 --> 00:06:41,360 Click next and this will give you a summary of the project you just created gives you all the details 83 00:06:41,380 --> 00:06:47,200 your path working directory top source level a device all that stuff. 84 00:06:47,260 --> 00:06:49,590 Go ahead and click Finish. 85 00:06:50,200 --> 00:06:52,260 And this is your project right now. 86 00:06:52,260 --> 00:06:58,330 It tells you when you got your father to project the device the FPGA we're targeting right here and 87 00:06:58,700 --> 00:06:59,980 there's nothing loaded in here. 88 00:06:59,980 --> 00:07:02,560 This is a completely blank project. 89 00:07:02,560 --> 00:07:11,120 So I want to go ahead and soak in the water to go to project and we're going to select Add at source. 90 00:07:11,140 --> 00:07:15,550 And that's because we've got a source of VHDL file that's already defined. 91 00:07:15,580 --> 00:07:21,820 Now if you're wanting to create a brand new VHDL file you can either a write the code and note external 92 00:07:21,820 --> 00:07:28,610 programs such as Notepad post-process or mulk or model Sam and bring it in like we're doing. 93 00:07:28,630 --> 00:07:33,940 Or you can go to a news source and if you do that you just want to select the VHDL module give it a 94 00:07:33,940 --> 00:07:37,690 file name collect next and it'll add it to your project. 95 00:07:37,690 --> 00:07:45,190 However we're not we are we've already got VHDL files we're using so we get a project at source and 96 00:07:45,190 --> 00:07:53,050 this is when I go back a level to our lab one folder we've got the FLATTR to VHDL file. 97 00:07:53,140 --> 00:07:56,270 I'm actually pick the VHDL file not the use File. 98 00:07:56,480 --> 00:07:59,820 So a slight That looks like open. 99 00:07:59,990 --> 00:08:00,800 OK. 100 00:08:01,300 --> 00:08:04,270 And there we have are four or two is in here. 101 00:08:04,270 --> 00:08:08,800 So if I double click on this it'll bring up your water to the HD. 102 00:08:08,800 --> 00:08:15,100 The VHDL file which is the same file we've seen in our notepad plus plus editors. 103 00:08:15,100 --> 00:08:22,450 Well now if you see these three little three three boxes here and like a triangle type shape thing. 104 00:08:22,450 --> 00:08:24,340 This is telling us a top level. 105 00:08:24,340 --> 00:08:31,990 So for example if I'm going to have a component instantiation and add another HDL file I want to make 106 00:08:31,990 --> 00:08:38,010 sure that there underneath this here which as we go when we have the use file you'll see how that it's 107 00:08:38,050 --> 00:08:38,560 done. 108 00:08:38,800 --> 00:08:45,580 So if I go ahead and I want to make sure that I select on my FLATTR project I'm going to outsource and 109 00:08:45,580 --> 00:08:47,190 this is where I want to select the U.S.. 110 00:08:47,280 --> 00:08:50,000 So go ahead and select Open. 111 00:08:50,510 --> 00:08:51,990 OK. 112 00:08:52,090 --> 00:08:54,980 And now it looks like you don't see that you see fall anywhere. 113 00:08:55,000 --> 00:09:01,390 That's because it's underneath this awful lot or two this is our top level this is the ultimate VHDL 114 00:09:01,390 --> 00:09:07,270 file if you will so if you expand on that you'll see it shows this water to your file. 115 00:09:07,270 --> 00:09:12,020 This just shows that this is tied to this for water to design file. 116 00:09:12,040 --> 00:09:21,510 So if I right click on this and I can double click it there and if you double click it you'll see your 117 00:09:21,510 --> 00:09:27,950 UCM file and you can kind of look at the syntax here and get the notation they've got going on. 118 00:09:28,110 --> 00:09:36,300 They've got their next scene which is defining your port member so this next scene is defining this 119 00:09:36,640 --> 00:09:45,010 see important member on the full letter too because an input standard logic and it's pointing into location 120 00:09:45,020 --> 00:09:56,750 PLN and so on the Spartan 3 FPGA pin 11 is associated with this scene and same for Seow same for x x 121 00:09:56,750 --> 00:10:05,750 y which this year you can type in here and edit this or you can you can use the if you click on your 122 00:10:05,750 --> 00:10:12,500 ECF you can edit the constraints to be attacks you can go here you go to your PIN planner which we don't 123 00:10:12,500 --> 00:10:14,090 need to because it doesn't. 124 00:10:14,240 --> 00:10:17,060 You can go this I hope I'm planning right click run. 125 00:10:17,090 --> 00:10:18,410 I'm not going to run through that. 126 00:10:18,440 --> 00:10:25,090 There's If you watch the video and the Xilinx section it goes through on how to do that. 127 00:10:25,310 --> 00:10:31,760 So I've already given you CFA So as of right now this project is complete we just have to synthesize 128 00:10:31,760 --> 00:10:34,330 and create a file. 129 00:10:34,370 --> 00:10:37,860 So in order to do that I go ahead and select my top level. 130 00:10:37,870 --> 00:10:41,260 If I don't I don't select it you'll see there's nothing available for me to do. 131 00:10:41,300 --> 00:10:43,840 As soon as I select it though I've got all these options. 132 00:10:43,850 --> 00:10:50,300 Now I want to go to implement design right click run and you'll see here it's going to run through the 133 00:10:50,300 --> 00:10:55,990 synthesis where it's got to translate it map it place and route. 134 00:10:57,040 --> 00:11:03,010 And this sometimes this is small design that won't take as long but some designs will get pretty big. 135 00:11:03,010 --> 00:11:08,330 This can take three to four minutes or more depending on how big your design is. 136 00:11:08,330 --> 00:11:13,340 So take all that and you might get some morning showing up like I get this warning saying my software 137 00:11:13,340 --> 00:11:20,200 subscription period is lapsed Tavor don't necessarily worry about that mapping place and route. 138 00:11:20,450 --> 00:11:24,710 And you get that green check mark that could just kind of shows that everything is working successfully. 139 00:11:24,880 --> 00:11:25,140 OK. 140 00:11:25,160 --> 00:11:30,020 So I feel like it's working I'm going to go ahead and right click on my generate programming file run 141 00:11:31,370 --> 00:11:36,700 and this is going to run through this is generating a bit stream. 142 00:11:36,920 --> 00:11:40,260 And this is what's actually the doc file we want to load. 143 00:11:40,420 --> 00:11:40,720 OK. 144 00:11:40,730 --> 00:11:43,170 So I went ahead and said that's successful. 145 00:11:43,190 --> 00:11:49,070 So right now this is if we go to our design summary it gives us all the information about this project 146 00:11:49,490 --> 00:11:55,090 tells you all the resources we've used the number of IPOs we've used etc.. 147 00:11:55,310 --> 00:12:01,010 So you can see right here we're pretty much just use 1 percent of all all these things here and about 148 00:12:01,010 --> 00:12:02,470 6 percent of the IO. 149 00:12:02,480 --> 00:12:05,480 There's 83 available we use 5. 150 00:12:05,600 --> 00:12:11,840 So that's it's useful information if you're before or even you can create your design and synthesize 151 00:12:11,840 --> 00:12:15,960 it and tell you if you need to step up to get a bigger device or whatever. 152 00:12:15,960 --> 00:12:17,930 So OK so I was right now. 153 00:12:17,930 --> 00:12:19,040 So Step two is completed. 154 00:12:19,040 --> 00:12:22,900 We've implemented our project and we've generated our bit file. 155 00:12:22,910 --> 00:12:25,510 Now we just need to put on the FPGA. 156 00:12:25,790 --> 00:12:34,170 So if we go ahead and bring up a dept we first need to do is make sure your base is to board the jumper 157 00:12:34,180 --> 00:12:40,070 JP 3 you have to make sure that it's selected the PC in order so it can connect to your computer because 158 00:12:40,070 --> 00:12:45,170 if not it's just going to read the information off of the flash chip but just look it on the FPGA. 159 00:12:45,620 --> 00:12:50,490 So once you are selected on PC plug it in your computer turn it on. 160 00:12:50,750 --> 00:12:55,470 Open up a dept and you'll see this and it's going to not identify anything. 161 00:12:55,490 --> 00:13:01,850 Click this initialize chain that recognizes your FPGA and your program will read only memory. 162 00:13:01,850 --> 00:13:05,500 We want to load directly onto the FPGA so we're going to use. 163 00:13:05,510 --> 00:13:13,760 Here we got to select our bit file browse and we've got to go to our desk top of one for our project 164 00:13:13,760 --> 00:13:20,540 and this is the bit file we generated and select Open and you'll get a warning about the clock. 165 00:13:20,540 --> 00:13:22,600 However you don't necessarily to worry about that. 166 00:13:22,700 --> 00:13:28,280 Go ahead and click yes click the program and give you no warnings. 167 00:13:28,280 --> 00:13:29,770 Go ahead and click yes. 168 00:13:30,020 --> 00:13:32,180 You'll see the video on your base two word flash. 169 00:13:32,180 --> 00:13:38,210 And as you can see down here it tells you that programming was successful and once you did that we've 170 00:13:38,210 --> 00:13:44,850 completed step three and once we get to this point you have successfully completed lab one. 171 00:13:44,980 --> 00:13:48,620 And now if you're ready go ahead and move on to the lab to.