WEBVTT 00:08.050 --> 00:14.650 Welcome to the latter but the basis the more I get to go ahead and do a full walkthrough and show you 00:14.650 --> 00:21.120 how to complete the quarter lab and program the basis for the first one to do is open up the Lovano 00:21.480 --> 00:28.370 you'll see what you have already downloaded and we'll go to create new project and this will bring a 00:28.370 --> 00:36.790 little wizard and go ahead and click on next in our project name we want to give it some sort of name 00:36.790 --> 00:38.040 to call it Project. 00:38.290 --> 00:44.490 I'm going to call it water to the. 00:45.130 --> 00:48.460 That's just because they're designed for working with his water too. 00:48.760 --> 00:53.830 And if you put your nose down we have the crate project subdirectory checked. 00:53.920 --> 00:59.410 That's because we want to get inside the folder create a separate folder that contains all of the projects 00:59.420 --> 01:02.650 just makes it easier to maintain and keep track of everything. 01:02.700 --> 01:04.790 So we're headed on next. 01:04.870 --> 01:10.240 And we want to select the RTL project where everything we're doing in this course will be using our 01:10.240 --> 01:13.300 genome project like next. 01:13.320 --> 01:18.990 And this is working at sources here is where you can add your FULL OUTER design file but we're actually 01:18.990 --> 01:23.260 going to do it later on to show you how to add it into the project after it's created. 01:23.360 --> 01:29.550 Make sure our target language is VHDL and our simulator language is mixed which doesn't matter we're 01:29.560 --> 01:32.760 not computing the simulator but just target what you want. 01:32.800 --> 01:42.720 The AGL misses us if we have any IP intellectual property and we go over look next and we don't have 01:42.720 --> 01:43.550 a constrained smile. 01:43.550 --> 01:47.120 We're going to add that after our next. 01:47.190 --> 01:49.210 Now we want to pick that apart. 01:49.410 --> 01:53.400 This is the FPGA that's located on the basis report. 01:53.430 --> 01:58.580 Now if we had certain boards we can suck on board and it gives us three different options there is that 01:58.600 --> 02:04.890 board seven nation platform in the seven direction and we're not using any of those. 02:04.890 --> 02:09.880 So if you are you would select one of these boards but we're using the basis three. 02:10.110 --> 02:16.940 So we're go to parks I mean go ahead and filter through our product category to get all the family want 02:16.950 --> 02:25.180 to select the Arctic 7 and the package is Sep g to 36. 02:25.240 --> 02:33.000 The grade is a dash 1 and that gives us three options here and we have on that basis the board is xes 02:33.260 --> 02:35.000 a 35 T. 02:35.050 --> 02:40.560 The second option that should be on your screen was like that just kind of gives you all of the available 02:40.560 --> 02:41.430 resources. 02:41.520 --> 02:42.920 We have turned 36. 02:42.930 --> 02:49.980 I know that the block RAM 90 the Espies so on and so forth you can just look through it gives you all 02:49.980 --> 02:53.220 the different characteristics of that part. 02:53.290 --> 02:59.100 We go ahead and slide next and it just gives you a summary overview of everything that's will be in 02:59.100 --> 03:02.010 the project go ahead and finish. 03:02.200 --> 03:05.560 And now it's going to go ahead and just give you the whole screen is telling you hey we're creating 03:05.560 --> 03:09.040 the project it's all files you'll need and everything. 03:09.150 --> 03:12.510 And so when you work with us here the vote will set. 03:12.540 --> 03:13.170 That's really nice. 03:13.170 --> 03:16.730 Everything has cost them line of the kind of guy you need how you want to go. 03:17.880 --> 03:23.970 Second notice right away we have your project summary which we don't have any files we don't have we 03:23.970 --> 03:26.400 haven't implemented or synthesize anything. 03:26.400 --> 03:28.240 So there's nothing really to show. 03:28.440 --> 03:32.850 The first thing we want to do is add our design source. 03:32.900 --> 03:40.470 We'll go ahead and write quick well design source and sources at source and we want to go ahead. 03:40.470 --> 03:45.170 It's like the second option add or create a design source. 03:45.240 --> 03:46.340 Next. 03:46.730 --> 03:51.200 We're going to go out and find the water to start the HD file. 03:51.210 --> 03:59.700 So a slight add file and I have it on my desktop but you want to go to the lab one file that you downloaded 04:00.260 --> 04:07.500 then inside of their lab one flatter go to the bases three directory and you should see a four letter 04:07.500 --> 04:10.260 to the HD file. 04:10.260 --> 04:15.440 It'll give you a little trial preview with phenolics like. 04:15.450 --> 04:17.850 And so when you go ahead it's like OK 04:20.880 --> 04:28.890 then and now make sure you have copy source in the project that way if you edit the actual file it will 04:28.900 --> 04:35.240 be inside your actual project so one to make sure you have copy sources and a product check and then 04:35.250 --> 04:37.170 go ahead and select finish. 04:37.600 --> 04:42.520 And you can see we have the full outer to our design source. 04:42.710 --> 04:47.140 So if you double click on it you'll see that it brings up a window that allows you to edit your files 04:47.150 --> 04:50.350 so we're going to make any changes we can do it inside of a video. 04:50.390 --> 04:54.520 So we'll see and next thing I want to do is add a constraint file. 04:54.570 --> 05:01.540 And this is what's going to tell us that this is what maps the port in our flat or to the actual Pendolino. 05:01.560 --> 05:06.390 And this is where we're going to say what are asked and see where what pins are going to be mapped to 05:07.260 --> 05:11.100 go ahead in like the constraints the sources. 05:11.300 --> 05:19.080 Right click and add sources is where want to select the first option and create constraints. 05:19.130 --> 05:23.520 What happens next in order to add files. 05:23.700 --> 05:32.940 And if you go to the same directory where we pulled the latter two types of files select design constraint 05:32.940 --> 05:39.200 files that gives us one option for one or two not accesory we select that that gives you a little preview. 05:39.330 --> 05:47.060 And this is what basically you're telling the design that here's where our production map to go and 05:47.080 --> 05:49.080 it's like OK. 05:49.080 --> 05:55.490 And then we'll make sure you check the copy constraints upon the project finish. 05:55.640 --> 06:00.300 And so right now we have everything we need to go ahead and create this project. 06:00.470 --> 06:06.290 So first up we want to do is that you'll notice on the left hand side of your screen that got the project 06:06.290 --> 06:11.400 manager IP integrator simulation RTL analysis synthesis. 06:11.390 --> 06:18.290 So we want to go ahead and click on the run synthesis button and this is going to go ahead and synthesize 06:18.290 --> 06:25.010 our design and make sure that all the VHDL code we have is understood by the compiler and it is what's 06:25.010 --> 06:26.100 going on. 06:26.100 --> 06:29.880 And if you notice in the top right hand corner of your screen it says running. 06:29.900 --> 06:34.570 Since this is designed we can go ahead and select wall. 06:34.820 --> 06:39.000 And this is just going to kind of go through and explain kind of what's going on and kind of see things 06:39.000 --> 06:39.850 as they happen. 06:40.130 --> 06:45.800 Make sure you got the license for it and it's selecting the Acura FPGA you chose and making sure all 06:45.830 --> 06:53.360 the off you have is with what what is allowed and play upon your computer this can take a little bit 06:53.360 --> 06:57.530 of time or it can go pretty quick which my computer will get older. 06:57.530 --> 07:05.150 So sometimes it's runs a little slower but you'll see it when it had to go and that now it's doing tiny 07:05.150 --> 07:10.610 optimization so it's going to basically go through and look at everything see your constraints file 07:10.760 --> 07:16.890 and everything that we have specified in or forward or to each file and actually map out make sure all 07:16.910 --> 07:22.690 the ports have selected and that there map too and everything is going on. 07:22.690 --> 07:24.870 It also tells you like you're different. 07:24.950 --> 07:27.910 Seek you how much time it's taken to run this. 07:28.020 --> 07:34.190 And it brings up a little message box message box for us to tell those our synthesis is complete and 07:34.250 --> 07:39.290 the next thing we want to do is run implementation and we can do it one of two ways we can like OK here 07:39.640 --> 07:40.880 which is what I want to do. 07:41.130 --> 07:46.550 So it's like OK and now it's going to go ahead and run the implementation and this is where it's actually 07:46.550 --> 07:51.050 going to take and route all of the signals on the actual FPGA. 07:51.140 --> 07:56.570 And if we didn't get a flight cancel or that box didn't come up well up inside you could cook on the 07:56.570 --> 07:58.420 run implementation. 07:58.420 --> 08:00.680 But once you have it running you don't want to click it again. 08:00.680 --> 08:01.640 So you just kind of wait. 08:01.700 --> 08:08.030 And you look in the top right hand corner you can see that it's saying ryme oft underscore design. 08:08.320 --> 08:13.600 And that's just telling you that's running the design figure out how to map everything. 08:13.760 --> 08:20.570 And if your select is on the bottom here it just kind of give you all messages about what it's doing 08:20.570 --> 08:25.840 and everything is happening and when you're not a memory it's using and so on and so forth. 08:25.850 --> 08:29.200 So we just can't wait until this is completed. 08:29.400 --> 08:35.060 If you have any problems in your design if you missed out something we come into the line now this is 08:35.060 --> 08:40.730 where it'll throw a warning or an error telling you that your design is wrong or anything else you've 08:40.730 --> 08:42.480 done something isn't right. 08:42.500 --> 08:48.050 So once you get past the implementation stage we'll go ahead and generate the bitstream which is what 08:48.050 --> 08:50.230 we're actually placed on here. 08:50.290 --> 08:55.170 E.J. so where it is basically is what it has to run. 08:55.220 --> 09:00.400 And when you get more complex designs this can take hours to do. 09:00.440 --> 09:02.630 You have a super complex design. 09:02.930 --> 09:06.490 You may have it may take three or four hours for this to run. 09:06.510 --> 09:10.580 While times will run these overnight an hour is done. 09:10.610 --> 09:12.070 So now we can open them. 09:12.180 --> 09:14.840 Design but we also don't need to open them. 09:14.840 --> 09:18.140 We're just going to go ahead and generate a bit string since we have no errors. 09:18.140 --> 09:20.840 We had a series of warnings that popped up. 09:20.900 --> 09:22.600 So go ahead and look. 09:22.820 --> 09:24.010 OK. 09:24.710 --> 09:27.200 And also that message doesn't pop up. 09:27.200 --> 09:31.600 You can just go to the left hand side of your screen and there's a general bitstream button. 09:31.670 --> 09:37.340 It's great out for me right now because I've already selected it to the pop up menu and you can see 09:37.340 --> 09:40.740 in the top right hand corner that it says running right that street. 09:40.960 --> 09:45.930 It's not actually taking everything and creating the actual file that we're going to load onto the bases 09:45.950 --> 09:55.630 pre-board and with the basic 3-D FPGA we here the bitstream is two megabytes which is what change. 09:55.770 --> 09:58.990 Whatever project you do you always have the same bitstreams size. 09:59.220 --> 10:03.620 And so we have a flatter or we have the 7 segment display. 10:03.660 --> 10:06.480 So have a 2 megabyte stream file. 10:06.780 --> 10:10.910 So it's just running through an OK. 10:10.940 --> 10:12.740 It'll let us know once it's popped up. 10:14.600 --> 10:19.210 Own you can see here in the law it's just kind of telling you what's going on it's creating a map frame 10:19.250 --> 10:26.750 bitstream that's writing it it's giving you the amount of memory use your stream has been completed 10:26.750 --> 10:28.070 successfully. 10:28.070 --> 10:35.270 So now we want to do is open the harbor manager using the reports and see what your resource utilization 10:35.270 --> 10:38.370 is what we'll do after we program more. 10:38.700 --> 10:41.510 Let's go ahead and select the open harbor manager. 10:41.540 --> 10:45.420 This is what we're going to use to actually program the basis for. 10:45.510 --> 10:47.890 So then select OK. 10:48.410 --> 10:50.880 And this is opens up a hardware manager. 10:51.000 --> 10:57.880 Now once when the harbor manager what we want to do is we want to connect freebasing stewpot. 10:57.930 --> 11:03.150 So this point I want to make sure that your basic storyboard is plugged in to your USP and it has to 11:03.150 --> 11:09.450 be in a port and has power over USD which you'll usually denoted by a little lightning bolt next year 11:09.450 --> 11:14.790 years before and you want to make sure your basic support is turned on and you should see the Red Tower 11:14.790 --> 11:18.860 Elodie on just to indicate that you have power on your board. 11:18.960 --> 11:22.970 So you go ahead and under Harbor manager we have this open target. 11:23.130 --> 11:28.970 We want to select that and we want to do things like open new target. 11:29.130 --> 11:34.170 If you've already connected to your bases seaboard you can select recent targets and it should be an 11:34.170 --> 11:36.270 option for starting your day. 11:36.300 --> 11:42.170 But we'll go ahead and open a new target and bring you up to a wizard that will guide you. 11:42.180 --> 11:46.660 We have nothing to our basis or Spanswick next. 11:46.940 --> 11:53.240 And we want to do local server that's because we're at the basis the board is connected to the PC that 11:53.240 --> 11:58.030 we're running here we're actually running on this machine we're not running on a remote server. 11:58.220 --> 12:05.610 Go ahead like next and it's going to go through and check and see what devices it can connect to. 12:06.050 --> 12:13.590 What you should see is that device here is Xilinx thesea digital and it's got a specific code on it. 12:13.720 --> 12:20.810 And if you just leave everything to default this X-C seven eight thirty five t that is the actual FPGA 12:20.810 --> 12:23.950 on the board and it's just saying that it recognizes it's there. 12:23.960 --> 12:27.420 So it's like next wizard. 12:28.560 --> 12:31.730 And then we can go ahead and finish. 12:32.220 --> 12:33.120 And it should. 12:33.180 --> 12:37.560 Now we're connected to the basic 3 board the hardware manager. 12:37.560 --> 12:45.060 And so we want to do is select a program device and it gives us the option of X-C 70 30 40 that's the 12:45.060 --> 12:48.800 FPGA is located on the basis of the board work on that. 12:48.870 --> 12:56.240 And we want to see like a bitstream file and just by nature the default is enough water to project and 12:56.280 --> 13:01.960 create its own directory structure so you can see we have this one or two project that called Dot runs 13:01.960 --> 13:05.630 slash implementation and the water to stop it. 13:05.910 --> 13:15.230 So go ahead and click program and we should see that the LCD base has three board in the top right corner 13:15.230 --> 13:18.950 of the Greenlees is done showing that the basis for the program. 13:18.950 --> 13:28.570 So now our full hour we can test it by going ahead and we have our C out and s are the first two ladies. 13:28.570 --> 13:35.340 So what we notice that is if I push one switch up I've got a binary one out that which tells me that 13:35.340 --> 13:38.140 OK I've got the single input. 13:38.190 --> 13:43.170 So if I get that one down and put another input in I still get a y output that tells me that I have 13:43.170 --> 13:44.690 one switched active. 13:44.700 --> 13:50.470 So out of the three on the right hand side is three switches I can play any combination those up in 13:50.480 --> 13:55.350 the sum of those inputs will be resolved on the ladies in binary format. 13:55.470 --> 14:02.920 So if I put the second one up I have a binary 2 which is a 1 0 up and the third one up or three. 14:02.940 --> 14:05.860 I have a binary 1 1 which is equal to 3. 14:05.870 --> 14:06.700 We're just kind of cool. 14:06.710 --> 14:08.300 I never went out. 14:08.310 --> 14:10.370 I still have a binary to go. 14:10.370 --> 14:15.020 I have to switch up all of the binary to which is a 1 0 5. 14:15.030 --> 14:16.610 Any one of the switches. 14:17.380 --> 14:20.190 Also I have just the finality of one. 14:20.220 --> 14:23.130 Same with the third switch. 14:23.450 --> 14:28.560 And so that is how the water works and that's essentially just kind of a run through of how you would 14:29.130 --> 14:35.850 create a project and bring in your VHDL files and your Excellency files and then go ahead and program 14:35.970 --> 14:37.440 your board and make sure it works.