1 00:00:01,060 --> 00:00:08,820 So welcome the module 8. to Xilinx ISC project and this module will be learning how to create a file 2 00:00:09,020 --> 00:00:17,390 that will be used to program our bases to board creating a project after you fire up Xilinx IAC. 3 00:00:17,550 --> 00:00:23,110 Go ahead and click on the new project button new project wizard. 4 00:00:23,190 --> 00:00:27,260 This will bring up the new project wizard for the name of your project. 5 00:00:27,270 --> 00:00:32,250 Use the name of the entity of your VHDL design for the location. 6 00:00:32,250 --> 00:00:37,330 Navigate to the directory where your VHDL design is located. 7 00:00:37,350 --> 00:00:43,680 Make sure to select HDL as your top level source type project settings. 8 00:00:43,740 --> 00:00:51,240 The next step in the wizard is disliked all the project settings the base bases to board FPGA as a Spartan 9 00:00:51,240 --> 00:01:03,270 3 device X C S One hundred E and Sep 1 3 2 package with the speed grade of Dash 4. 10 00:01:03,360 --> 00:01:08,360 Select the VHDL synthesis tool and the ice simulator. 11 00:01:08,460 --> 00:01:14,400 We're using the VHDL 93 standard project summary. 12 00:01:14,430 --> 00:01:19,230 Once you have completed the new project wizard the project summary will be shown. 13 00:01:19,230 --> 00:01:23,700 This report will give you all the settings of the project we just created. 14 00:01:23,700 --> 00:01:29,010 Click Finish to create the project add design file. 15 00:01:29,010 --> 00:01:31,250 Your screen should look something like this. 16 00:01:31,260 --> 00:01:35,880 Select the implementation radio button in the View section. 17 00:01:35,880 --> 00:01:45,670 This is where you load our VHDL design file to project at source and this will bring up a dialog box. 18 00:01:45,780 --> 00:01:52,460 Navigate to the VHDL design file you are wanting to load onto the FPGA. 19 00:01:52,490 --> 00:02:00,030 No if you haven't already coded your VHDL file in Notepad post plus or other text editor you can select 20 00:02:00,180 --> 00:02:10,010 the new source and select VHDL file and code the design file in the ISC tool for that two example. 21 00:02:10,320 --> 00:02:16,800 If you don't click on the VHDL file in your project this is what your screen should look like. 22 00:02:16,800 --> 00:02:23,680 Note that the entity of the VHDL file is the same name of the ISC project. 23 00:02:23,790 --> 00:02:30,460 Also no the three squares that indicate your VHDL file is set as the top level. 24 00:02:30,540 --> 00:02:34,050 You can only have one top level VHDL file. 25 00:02:34,230 --> 00:02:40,980 If you have multiple VHDL files in it design the top level would contain component instantiations of 26 00:02:40,980 --> 00:02:43,270 all the other VHDL files. 27 00:02:44,130 --> 00:02:45,000 Map the. 28 00:02:45,110 --> 00:02:55,660 So the next step is to map the FPGA to the IDE to in our VHDL design make sure you have saved any edits 29 00:02:55,660 --> 00:03:02,830 to the VHDL file right click once on the top level VHDL design file to activate it. 30 00:03:03,070 --> 00:03:08,640 Then right click on the IO planning priest synthesis option and select Run. 31 00:03:08,820 --> 00:03:12,220 Note that for all the projects you will be completing. 32 00:03:12,250 --> 00:03:15,540 I'll provide you with the necessary user constraints file. 33 00:03:15,610 --> 00:03:19,540 So you only have to focus on the FPGA development portion. 34 00:03:19,540 --> 00:03:24,380 However if you're wanting to create your own designs this is a great reference for you. 35 00:03:25,500 --> 00:03:32,710 The following two dialog boxes may appear the first dialog box will appear. 36 00:03:32,760 --> 00:03:38,470 If you do not have a user constraints file inside of your project go ahead and click yes. 37 00:03:38,550 --> 00:03:45,810 Xilinx is just informing us that they will be adding a user constraints file or you CEF file to our 38 00:03:45,810 --> 00:03:47,520 project. 39 00:03:47,520 --> 00:03:55,800 This file is used to tell the compiler what FPGA pins are tied to what VHDL entity poor members. 40 00:03:55,830 --> 00:04:00,280 The next dialog box is warning you that you will be editing the same. 41 00:04:00,360 --> 00:04:06,890 You C-f from the IAC project we are currently have open and the new program we are currently opening. 42 00:04:06,900 --> 00:04:09,530 Go ahead and click yes. 43 00:04:09,600 --> 00:04:10,680 Plan ahead. 44 00:04:10,680 --> 00:04:14,510 This will bring up the Xilinx plan ahead tool showing your screen. 45 00:04:14,580 --> 00:04:19,580 The only part we are concerned with is the port section and the upper left hand side. 46 00:04:19,830 --> 00:04:26,550 Note that all the inputs and outputs specified an entity of your VHDL design should show up in this 47 00:04:26,550 --> 00:04:27,310 section. 48 00:04:29,170 --> 00:04:35,470 Here is you showing the entity VHDL design and the Plan ahead screenshot. 49 00:04:35,470 --> 00:04:41,770 Notice that the inputs and outputs of the entity match up with the available inputs and outputs we have 50 00:04:41,770 --> 00:04:46,520 available to map physical FPGA pins to and plan ahead. 51 00:04:46,720 --> 00:04:53,680 This is because the entities section are VHDL design tells us how our design interacts with the outside 52 00:04:53,680 --> 00:05:02,180 world which in this case pins on an FPGA in order to determine what entity ports need to connect to 53 00:05:02,180 --> 00:05:03,950 what pends referred to. 54 00:05:03,950 --> 00:05:10,790 The base is to use your guide where you will find and see your six figure six shows you what pins are 55 00:05:10,790 --> 00:05:21,590 connected to each peripheral for the for example will be using switch 0 1 and 2 for inputs X Y and C 56 00:05:21,590 --> 00:05:28,460 in these peripherals are connected to pins 11 L-3 and K3. 57 00:05:28,630 --> 00:05:34,950 So the output C and S will be using the Ltd's as indicators. 58 00:05:35,000 --> 00:05:42,870 The FPGA pins and M5 and 11 are connected to 0 and 1 which are the LDS. 59 00:05:42,880 --> 00:05:44,320 We will be utilizing. 60 00:05:44,600 --> 00:05:48,790 You should be able to see this reflected in the figure on the right. 61 00:05:48,800 --> 00:05:52,840 Now go ahead and click save and close out of plan ahead. 62 00:05:52,880 --> 00:06:00,140 You if user constraints file when you go back to your ISC project you should see your newly created 63 00:06:00,410 --> 00:06:02,690 U.S. file as shown. 64 00:06:02,690 --> 00:06:09,000 Double click on it and you can pretty easily pick up on the formatting if you want to create new U.S. 65 00:06:09,140 --> 00:06:09,880 files. 66 00:06:10,010 --> 00:06:13,580 You can use any text editor and following the pattern. 67 00:06:13,580 --> 00:06:15,980 Create your own you see files. 68 00:06:16,160 --> 00:06:22,430 However the nice thing about using plan ahead is that it only allows you to pick valid IO pins and you 69 00:06:22,430 --> 00:06:29,410 cannot pick the same pin twice implement in design and generate programming file. 70 00:06:29,570 --> 00:06:35,240 The final step is to implement our design and generate the programming file in order to do this. 71 00:06:35,240 --> 00:06:37,700 Right click on implement design. 72 00:06:37,700 --> 00:06:38,460 Run. 73 00:06:38,480 --> 00:06:41,000 This may take a few minutes to complete. 74 00:06:41,030 --> 00:06:44,630 Then right click on generate programming file run. 75 00:06:44,630 --> 00:06:48,210 This also can take a few minutes after this is completed. 76 00:06:48,230 --> 00:06:53,920 You can look in your projects directory and you should see a B tif file. 77 00:06:53,930 --> 00:07:02,000 This is a file you'll be loading onto the FPGA final report after your program file has been generated 78 00:07:02,330 --> 00:07:08,020 airport giving you all the information regarding to how many Io's you have used. 79 00:07:08,030 --> 00:07:14,800 How much logic your design has used up and an overall summary of your project summary. 80 00:07:14,870 --> 00:07:19,360 We have just completed module eight point two Xilinx ISC project. 81 00:07:19,350 --> 00:07:26,140 Here is a summary of everything we whenever we can use Plan ahead instead of Xilinx ISC to create. 82 00:07:26,140 --> 00:07:29,010 Are you C-f user constraints file. 83 00:07:29,270 --> 00:07:38,480 You import VHDL files into Xilinx IAC or even create them using the integrated VHDL editor Xilinx IAC 84 00:07:38,480 --> 00:07:43,970 is a tool we will be using to generate a program file to load onto our FPGA.