WEBVTT 00:00.930 --> 00:10.740 Welcome to module 8.1 Xilinx I assume Xilinx I assume Xilinx I assume is a tool you can use to simulate 00:10.740 --> 00:12.440 your VHDL designs. 00:12.690 --> 00:16.590 I see them as built into Xilinx IAC tool. 00:16.580 --> 00:23.790 We will be using Altera in order to give you more exposure to both Xilinx and Altera tool sets creating 00:23.790 --> 00:28.410 an AI sim simulation in order to create an awesome simulation. 00:28.410 --> 00:35.730 Cray is Xilinx IAC project as you normally would just be sure to specify that you want to use the sim 00:35.730 --> 00:38.550 simulator as shown on your screen. 00:39.210 --> 00:49.020 Adding a testbench coach project new source VHDL testbench give your testbench a name and then click 00:49.020 --> 00:53.200 next associate design file. 00:53.220 --> 00:57.510 Next you need to associate a design file with this testbench. 00:57.540 --> 01:02.620 Select the VHDL design file you want to test click next. 01:02.670 --> 01:10.080 Then you should see a summary of the testbench you created checks and tags select the testbench and 01:10.080 --> 01:11.090 then click. 01:11.100 --> 01:15.140 Right click on the debt on the checks and tax and then select Run. 01:15.390 --> 01:20.490 If there are errors in the testbench you'll see them show up in the errors tab at the bottom of your 01:20.490 --> 01:21.700 screen. 01:22.240 --> 01:23.970 Insert stimulus. 01:24.150 --> 01:31.290 You will need to modify the testbench in order to place a stimulus on the inputs of your VHDL design 01:31.290 --> 01:32.970 file. 01:33.060 --> 01:40.290 Run your simulation first make sure your test bench is selected then right click on the simulate and 01:40.290 --> 01:44.880 then select Run verify results. 01:44.880 --> 01:49.170 Now you need to verify that the outputs are what you were expecting. 01:49.170 --> 01:56.060 If they're not then you need to modify your VHDL design file and rerun the simulation. 01:56.330 --> 02:00.090 You have just completed module 8.1 I assume. 02:00.090 --> 02:02.780 Here's a summary of the things we went over. 02:02.820 --> 02:09.990 I assume as a VHDL simulation tool that Xilinx provides you can directly integrate your ICM simulation 02:09.990 --> 02:12.620 projects with your IAC design.