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Welcome to module 8.1 Xilinx I assume Xilinx I assume Xilinx I assume is a tool you can use to simulate

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your VHDL designs.

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I see them as built into Xilinx IAC tool.

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We will be using Altera in order to give you more exposure to both Xilinx and Altera tool sets creating

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an AI sim simulation in order to create an awesome simulation.

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Cray is Xilinx IAC project as you normally would just be sure to specify that you want to use the sim

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simulator as shown on your screen.

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Adding a testbench coach project new source VHDL testbench give your testbench a name and then click

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next associate design file.

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Next you need to associate a design file with this testbench.

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Select the VHDL design file you want to test click next.

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Then you should see a summary of the testbench you created checks and tags select the testbench and

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then click.

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Right click on the debt on the checks and tax and then select Run.

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If there are errors in the testbench you'll see them show up in the errors tab at the bottom of your

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screen.

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Insert stimulus.

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You will need to modify the testbench in order to place a stimulus on the inputs of your VHDL design

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file.

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Run your simulation first make sure your test bench is selected then right click on the simulate and

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then select Run verify results.

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Now you need to verify that the outputs are what you were expecting.

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If they're not then you need to modify your VHDL design file and rerun the simulation.

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You have just completed module 8.1 I assume.

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Here's a summary of the things we went over.

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I assume as a VHDL simulation tool that Xilinx provides you can directly integrate your ICM simulation

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projects with your IAC design.