1 00:00:02,820 --> 00:00:09,000 In this lecture, we are going to instantiate an ally in the parallel to surreal, to parallel design 2 00:00:09,240 --> 00:00:15,570 and monitor some of the design signals and runtime while the circuit is running inside the FPGA on the 3 00:00:15,570 --> 00:00:15,840 board. 4 00:00:19,640 --> 00:00:22,460 We customize the aioli to have seven problems. 5 00:00:23,900 --> 00:00:27,110 This table shows the design signals connected to each. 6 00:00:28,250 --> 00:00:34,640 As can be seen, the first on six probes have Apitz and the others have only one bit. 7 00:00:40,260 --> 00:00:46,020 First, open the parallel to Sariel to parallel, if you are the project explained earlier in this course, 8 00:00:46,920 --> 00:00:48,540 it consists of two ities. 9 00:00:49,550 --> 00:00:55,910 The establishment is connected to its light switches and the board and the begin conversion is directly 10 00:00:55,910 --> 00:00:56,930 connected to a push. 11 00:00:56,930 --> 00:01:04,310 But we now know that to connect the push button switch to digital system, we needed the bouncer and 12 00:01:04,310 --> 00:01:08,150 probably a pulse generator IP depending on our design. 13 00:01:09,070 --> 00:01:12,580 So let's modify the design and add those ipis. 14 00:01:15,910 --> 00:01:19,550 You can find the IPS in the resources folder attached to this selection. 15 00:02:21,490 --> 00:02:28,180 Now, at an L.A. EPEAT to the diagram area, in order to use this IP, we have two steps here. 16 00:02:28,570 --> 00:02:32,050 Customize the IP and connect the IP to the design. 17 00:02:32,590 --> 00:02:37,710 First of all, determine the signals that you are going to monitor later at runtime. 18 00:02:38,830 --> 00:02:42,010 We can connect the Ilic input to the design clock. 19 00:02:42,520 --> 00:02:45,070 This clock is used for data sampling. 20 00:02:46,160 --> 00:02:47,330 Let's customize the. 21 00:02:49,430 --> 00:02:54,050 Double click on Dial IP to open the customize IP window. 22 00:02:55,310 --> 00:02:59,150 First of all, choose the native as the monitor type. 23 00:03:00,610 --> 00:03:08,080 Then determine the number of props, which is the number of design signals for monitoring, for example, 24 00:03:08,230 --> 00:03:09,010 seven here. 25 00:03:10,140 --> 00:03:15,500 Then we should configure the probes, go to the probe, underscore reports that. 26 00:03:16,440 --> 00:03:22,770 Here, attached to each port, there are three Parramatta's two of them are important for us in this 27 00:03:22,770 --> 00:03:26,380 cause profit and pop trigger date. 28 00:03:27,330 --> 00:03:32,670 The first problem is going to be connected to the air input, which has eight bits. 29 00:03:33,240 --> 00:03:38,100 The other probes have one bit except Prop five, which has eight bits. 30 00:03:57,400 --> 00:04:04,900 After defining the prop bit with we should define which probes are used for trigger and which ones for 31 00:04:04,900 --> 00:04:05,320 data. 32 00:04:05,620 --> 00:04:14,110 Alternatively, we can keep the defaults in which probes can be used for data and trigger at runtime. 33 00:04:14,350 --> 00:04:17,440 We choose some probes to make the trigger signal. 34 00:04:27,670 --> 00:04:29,860 Now we can make the connections. 35 00:04:59,430 --> 00:05:05,040 Then we should create the ideal rapport and generate down put products and the bitstream. 36 00:05:19,720 --> 00:05:26,620 OK, here we have an another situation, if you go to the message that we can read the error message 37 00:05:28,630 --> 00:05:31,750 as I'm running the Vado on their Windows OS. 38 00:05:32,750 --> 00:05:38,830 It complains about some files and directory paths longer than one hundred and sixty two characters, 39 00:05:40,040 --> 00:05:44,110 if you are using Linux OS, you want see this message. 40 00:06:03,850 --> 00:06:09,370 Just move the project to a directory with the shorter path and generate the with three mega. 41 00:06:33,880 --> 00:06:41,230 Now programmed, bought the device automatically opens the aisles away from window here, we should 42 00:06:41,230 --> 00:06:42,690 define the trigger condition. 43 00:06:45,620 --> 00:06:52,250 And boolean expression can be used to define the trigger condition, click on the icon, then select 44 00:06:52,250 --> 00:06:57,020 the only signal defined as a trigger signal during LRIP customization. 45 00:06:57,470 --> 00:07:00,350 Now we should define the boolean expression here. 46 00:07:00,500 --> 00:07:06,710 The Boolean expression is very simple and we are going to start the monitoring process when the signal 47 00:07:06,710 --> 00:07:07,120 is one. 48 00:07:07,520 --> 00:07:10,850 So the operator is equality and the value is one. 49 00:07:14,840 --> 00:07:22,550 Now we can start the dialogue, we'll start the monitoring process and wait on a high logic value on 50 00:07:22,550 --> 00:07:25,310 the pulse generated by the pressing the push button. 51 00:07:26,200 --> 00:07:32,080 Just press the push button on the board, and after a few seconds, what's this signal wave form in 52 00:07:32,080 --> 00:07:33,690 the L.A. pay phone window? 53 00:07:34,840 --> 00:07:39,760 This is the binary pattern that I have set on the slide switches as the input to the. 54 00:07:52,410 --> 00:07:57,630 As this video is the last lecture in the section that explains the design idea and techniques, the 55 00:07:57,630 --> 00:08:03,690 next lecture will give you a few exercises to practice what you have learned throughout this section. 56 00:08:07,400 --> 00:08:14,210 These are our takeaway messages, dialing IP can be added to our design in Vado for runtime debugging. 57 00:08:15,160 --> 00:08:17,860 The trigger condition is defined at runtime. 58 00:08:19,260 --> 00:08:24,000 If you are using the Windows OS, be aware of the Project Pampling. 59 00:08:27,440 --> 00:08:34,220 Now, the quiz question, what would happen if you accept the default value for Propter, your data 60 00:08:34,370 --> 00:08:40,130 during the Iola customization, notice that the default value is data and trigger.