1 00:00:01,740 --> 00:00:07,620 How can we debug our design after programming the FPGA, this lecture will explain how to debug our 2 00:00:07,620 --> 00:00:10,320 design inside an FPGA at runtime. 3 00:00:13,610 --> 00:00:19,000 Monitoring the design port signals on the board is usually the last step of debugging a design. 4 00:00:20,620 --> 00:00:24,670 This monitoring is usually done by using a logic analyzer. 5 00:00:25,740 --> 00:00:33,210 However, physical logic analyzers are usually very expensive and may not be accessible in some situations 6 00:00:33,870 --> 00:00:35,350 to cope with this issue. 7 00:00:35,490 --> 00:00:41,310 We Vado provides an integrated logic analyzer, Ioway IP for this purpose. 8 00:00:42,030 --> 00:00:49,770 The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of 9 00:00:49,770 --> 00:00:50,310 a design. 10 00:00:50,520 --> 00:00:58,320 Dialectal includes many advanced features of modern logic analyzers, including boolean trigger equations 11 00:00:59,010 --> 00:01:00,990 and age transition triggers. 12 00:01:01,650 --> 00:01:08,970 Because the L.A. is synchronous to the design being monitored, all design clock constraints that are 13 00:01:08,970 --> 00:01:13,830 applied to your design are also applied to the components inside dialectal. 14 00:01:16,620 --> 00:01:24,980 Signals in an FPGA design can be connected to these signals attached to the probe, inputs are sampled 15 00:01:24,990 --> 00:01:29,550 and design speed and stored using a chip block from Beera. 16 00:01:30,790 --> 00:01:37,250 The core parameters are specified, the number of probes to sample depth and the width of each probe 17 00:01:37,270 --> 00:01:45,130 input communication with dialectal is conducted using an auto instantiated DeBacker that connects to 18 00:01:45,130 --> 00:01:47,590 the geotag interface of the FPGA. 19 00:01:51,970 --> 00:01:58,720 And I UNICOR has several input and output ports in this course, we only use the basic ones. 20 00:01:59,890 --> 00:02:04,690 Dialla needs a clock to synchronize its functionality and data sampling. 21 00:02:04,840 --> 00:02:11,680 With the design on their test, a set of customizable ports will be connected to design signals under 22 00:02:11,680 --> 00:02:12,240 inspection. 23 00:02:13,990 --> 00:02:17,720 There are other ports which are not our concerns in this course. 24 00:02:20,360 --> 00:02:24,780 L.A. can provide up to one thousand twenty four props. 25 00:02:26,970 --> 00:02:33,750 Each group can have up to four thousand ninety six bits, in addition, each group can be customized 26 00:02:33,750 --> 00:02:36,180 as data trigger or both. 27 00:02:37,580 --> 00:02:45,710 And Iola consists of two main components, a sampling circuit only Bira, the sampling circuit samples, 28 00:02:45,710 --> 00:02:49,640 the signals connected to data and saves them in the bira. 29 00:02:51,660 --> 00:02:58,170 The size of Biram is defined by sample data or depth parameter, representing the maximum number of 30 00:02:58,170 --> 00:03:02,250 samples that can be stored at runtime for each probe in. 31 00:03:03,470 --> 00:03:09,410 Notice that the number of samples is limited by Behram size left for L.A. in an RPG. 32 00:03:12,920 --> 00:03:19,550 We need the mechanism to define the start of sampling the trigger logic circuit provides this triggering 33 00:03:19,550 --> 00:03:20,030 mechanism. 34 00:03:20,210 --> 00:03:26,030 This logic circuit receives a set of inputs through probes that are defined as a trigger type. 35 00:03:27,410 --> 00:03:33,710 These three airports are combined using a boolean expression to generate a trigger signal that feeds 36 00:03:33,710 --> 00:03:34,670 the sampling circuit. 37 00:03:36,000 --> 00:03:42,720 Notice that regular FPGA logic is used to implement the sampling and trigger functionality, therefore 38 00:03:42,870 --> 00:03:47,400 there should be enough resources available on the PGA for both design and. 39 00:03:52,580 --> 00:03:55,160 And the usage has two main steps. 40 00:03:57,160 --> 00:04:03,970 The first that happens during design time and another happens during runtime when the FPGA runs the 41 00:04:03,970 --> 00:04:11,380 application during the design time, if you initialize the IP, customize that and finally connect that 42 00:04:11,380 --> 00:04:12,610 to the design signals. 43 00:04:12,910 --> 00:04:21,310 Customization process includes defining the number of ports Turbit with and also defining the sample 44 00:04:21,310 --> 00:04:24,020 data depth that determines that Behram size. 45 00:04:24,730 --> 00:04:28,900 There are also some advanced features that are not covered in this course. 46 00:04:31,760 --> 00:04:37,430 After the design is loaded into the FPGA, we use the reverse the logic analyzer software to define 47 00:04:37,430 --> 00:04:38,840 the trigger boolean expression. 48 00:04:39,830 --> 00:04:46,220 After the trigger occurs, the sample buffer is filled and uploaded into the device, the logic analyzer. 49 00:04:46,880 --> 00:04:49,980 You can view this data using the waveform bindle. 50 00:04:53,850 --> 00:05:00,450 How can we use an ally in a real design, the next lecture will add an ally to the parallel, to surreal, 51 00:05:00,450 --> 00:05:07,890 to parallel design explained earlier in discourse, and will show the design signal waveforms at runtime. 52 00:05:14,450 --> 00:05:16,040 These are our takeaway messages. 53 00:05:18,290 --> 00:05:26,180 And integrated logic analyzer IP can monitor design signals at runtime and isolate samples of selected 54 00:05:26,180 --> 00:05:32,630 design signals and saves the data in Beera inside the FPGA to be used later for monitoring. 55 00:05:33,320 --> 00:05:38,650 The customization is the first step of using an in a design trigger. 56 00:05:38,660 --> 00:05:43,340 Conditions should be defined at runtime to determine the start of data sampling. 57 00:05:48,250 --> 00:05:53,320 Now, the quiz question, what is the role of the input signal in an era like?