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How can we generate a single cycle, regular pulses with a given period?

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This lecture will cope with this question.

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The single cycle regular generator receives a clock with the period of and generates another clock with

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the period of TP in which the high state is only one cycle of the input clock.

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And denotes the number of design or input clock cycles that fits in a period of the output clock.

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And it can be calculated by dividing the TPE to take the output signal should be in the high level voltage

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for one clock cycle.

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And it should be in the low level voltage for N minus one clock cycles.

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Let's write the code, we assume there are 20 clock cycles in the output pulse part that is and is 20.

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The circuit has two states, zero and one corresponding to the output clock logic values, the design

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of function has one argument, which is the output node, that the design clock will be added to the

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circuit by their is to.

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We should add port interfaces.

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Now we need a static variable synthesized into a register to save a design state.

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Also, we did a static variable to count the number of input clock cycles, according to our coding

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style, describing a state machine.

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We need a temporary variable corresponding to each register that keeps track of intermediate values

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for registers throughout the state machine.

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Similarly, we define a temporary variable for the output.

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Now we should describe our state machine and after that, the registers and the output ports should

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be updated.

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The state machine has two states, the second should be and minus one clock cycles in the 08 state and

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only one caucus cycle in the state as can be seen, the 08 state starts the counter from polls underscore

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period minus one and decrements that on each clock cycle, when the counter is one, the state machine

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goes to state one to spend one clock cycle.

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Then it goes back to the zero state.

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Let's check the design, invite Satchel's.

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Create a new White House project with the name of single underscore cycle, underscore, regular, underscore

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Pulsers Dash Wiki suchness.

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Choose the basis three as a target of.

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Download the design and test bench fines from the resources attached to this lecture and add them to

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the project's.

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Now, let's have a look at the coats we saw the design Sourcefire earlier in this lecture.

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The test bench phone calls are designed to function 100 times and print the output argument on the screen

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each time.

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Now we can perform the simulation.

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Know that our design follows a single cycle design approach, the result shows that the output signal

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is zero for 19 clock cycles and is one for one clock cycle on each part.

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By synthesizing our code, we can make sure that the result of the article description is a single cycle

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designed for this purpose.

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Please have a look at the analysis perspective.

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Now, let's part on the R TLC simulation.

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Don't forget to select the all option in the dumped race feature.

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After finishing the simulation process, click on The Open Viewer.

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So the design out to Don Clark signals in the event of a viewer.

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And check the output signal, period and pulse.

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How to detect edges on an input signal, the next lecture will answer this question.

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This is our takeaway message, using a counter can help in some designs to determine the number of clock

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cycles that a state machine should stay in each state.

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Now, the quiz question modified the code in a single cycle, regular pulses, top function and generate

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the following signal.