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FPGA boards usually provide the high speed clock signal, however, in some designs, we need a slower

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clock signal.

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Now, the question is, how can we generate this lower class signal based on the highest bidder bid

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FPGA O'Rourke, this section will answer this question.

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The idea of generating a slower clock with a frequency of slow from a fast clock with the frequency

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of fast is using a clock division circuit.

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Therefore, if the design clock frequency is a fast, then we can divide the frequency by 10 to generate.

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For example, if fast is one hundred megahertz and is 1000, then flow is hundred kilohertz.

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This diagram shows the relation between the design signal and the output of the clock generate or clock

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during.

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As can be seen, the output signal has to logic levels zero and one, our circuit also has two states

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corresponding to these logic levels the circuit, the states in each state four and divide by two clock

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cycles and then goes to the next state.

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Now, let's try the code for a generator circuit that generates five megahertz signal from 100 megahertz

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design clock.

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In this case, and is one hundred divided by five, which means 20.

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The of the designed clock is 10, 10:00, therefore, the period of the generated clock would be 200

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nanoseconds.

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The clerk's duty cycle is 50 percent, if it is in the logic level, one half of it's.

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For writing the actual code, create a new White House project with the name of Klok underscore generator

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dash want to select the clock underscored generator as a design top function.

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Don't forget to choose the basic storyboard as a target FPGA.

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And the design source folder create a design source and Heather Fart's also create the test bench in

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the test bench for.

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Upon the design, Sourcefire and defined the clock, underscore frequency, underscore deviser, macro

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and enumeration data type that contains the circuit states which are zero and bar.

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The design to function has only one output argument let's define the interfaces now.

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We should define a register to represent the sum of the states, let's initialize that with zeal.

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We also need to register with the name of counter that keeps track of clock cycles, and its initial

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value is one less than half of the clock frequency devi's.

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Following our single cycle design flaw, we should define two temporary variables to keep the counter

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and the state's intermediate values in the circuit state machine.

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Also, we need a temporary variable corresponding to the output argument.

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Now we can use a two state state machine to describe the behavior of the circuit.

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The state represents the time that the output is zero and the one state represents the time that the

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output is one.

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The country states half of its period in each state, the county register helps to keep track of the

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number of cycles in each state.

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When the circuit is in zero state, it decrements the counter on each clock cycle and when the counter

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gets to zero, the circuit goes to state one while the counter is set to one less than the half of the

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counter frequency.

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The value.

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The same behavior happens when the circuit is in a state one.

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After the state machine, we should modify the registers and update the.

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Now, let's try to test code.

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OpenNet has been shattered by another design, top function prototype.

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As we use the circuit for generating the output clock signal, the test bench file only calls the design

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one hundred times.

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Now we can perform the simulation.

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Downwith, printed on the screen, shows that the second output is ten times one and 10 times zero.

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This means the frequency of the output is one twentieth of the designed frequency.

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Now perform the high level syntheses task and check that the description is synthesized into a single

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cycle RTL code.

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After finishing the sentence, he successfully performed the archaeological simulation and selling all

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for the country's future.

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Now click on the Open Viewer IRC.

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Delivered away from the air will be opened.

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Showed the second output signal and Checketts Pariente.

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For triggering some circuits, we usually need a single cycle pulse, how can we generate a single cycle

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pulse in the next lecture?

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We'll address this question.

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This is our takeaway message, using a collective either circuit, the kind of scale, the designed

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frequency to generate a slower clock.

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Now, the quiz question, if you check the revised away form carefully, you can see that the recent

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signal doesn't have any impact on the circuit act, modify the project setting to reset the circuit

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output with the designers that signal.