1 00:00:01,700 --> 00:00:05,610 How could design a digital circuit for counting a sequence of events? 2 00:00:06,230 --> 00:00:08,270 This section will call for discussion. 3 00:00:11,880 --> 00:00:19,600 A counter is a device that can counter sequence of events or objects, a digital counter usually counts 4 00:00:19,610 --> 00:00:21,070 a sequence of pulses. 5 00:00:21,700 --> 00:00:28,000 Therefore, if a sensor converts the sequence of objects or events to a sequence of pulses, the digital 6 00:00:28,000 --> 00:00:29,200 counter can be used. 7 00:00:29,760 --> 00:00:36,370 A synchronous counter receives the clock along with a set of inputs and generates a set of outputs. 8 00:00:38,710 --> 00:00:47,020 Inputs can be reset that sets the counter to zero enable that allows or inhibits counting direction 9 00:00:47,020 --> 00:00:52,190 that determines whether the counter will increment or decrement data. 10 00:00:52,390 --> 00:00:59,710 That is a parallel input data, which represents a particular counter value load that copies parallel 11 00:00:59,710 --> 00:01:01,270 input data to the count. 12 00:01:02,890 --> 00:01:05,380 There are several types of counters here. 13 00:01:05,500 --> 00:01:11,560 We are going to design a single digit VCT up counter that receives a pulse and generates signals for 14 00:01:11,560 --> 00:01:18,310 a seven segment display, regardless of the pulse with the counter increments, the output when it receives 15 00:01:18,310 --> 00:01:18,860 the pulse. 16 00:01:19,570 --> 00:01:24,190 The counter counts from zero to nine and then gets back to zero. 17 00:01:28,020 --> 00:01:34,230 Creative writers such as Project with the name of Counter Dash, White Essentialists, selective basis 18 00:01:34,230 --> 00:01:40,650 to report as the FPGA platform, then create to design files and to test bench finds. 19 00:02:08,200 --> 00:02:16,210 Open the design header file, include the AP underscore in that file and define a constant array containing 20 00:02:16,210 --> 00:02:19,510 the seven segment code for digits from zero to nine. 21 00:02:20,020 --> 00:02:23,170 Save the file and then open the design source file. 22 00:02:24,040 --> 00:02:30,460 Our counter should detect a pulse on its input so it should first detects the transition from zero to 23 00:02:30,460 --> 00:02:32,820 one and then increment the counter. 24 00:02:33,280 --> 00:02:39,100 It should then detect the transition from one to zero and get ready for the next pulse on the input 25 00:02:39,100 --> 00:02:39,520 signal. 26 00:02:40,030 --> 00:02:46,300 Therefore, the design has to estates, let's call them, wait for one and wait for zero. 27 00:02:47,660 --> 00:02:50,120 This design has one input and two outputs. 28 00:02:50,690 --> 00:02:53,680 It's a good practice to define the argument interfaces. 29 00:02:53,720 --> 00:03:01,070 Right now we need to define two registers, one to give the current number of the counter. 30 00:03:02,050 --> 00:03:08,100 And the second to keep track of the circus states, then corresponding to each register, we define 31 00:03:08,110 --> 00:03:08,800 a variable. 32 00:03:09,490 --> 00:03:13,330 Now let's define the two each case to describe the FSM transitions. 33 00:03:13,810 --> 00:03:17,840 The switch statement has two cases corresponding to two states. 34 00:03:18,830 --> 00:03:23,800 Initially, we are in the wait for one state when the count button is one. 35 00:03:24,840 --> 00:03:31,110 We commend the next number of valuable and go to the wait for zero state, otherwise we stay in the 36 00:03:31,110 --> 00:03:34,350 wait for one state, in the wait for zero state. 37 00:03:34,350 --> 00:03:39,810 As long as the input is one we stay in that state when they are level zero is received. 38 00:03:40,590 --> 00:03:45,810 The FSM goes to wait for one state ready for the next input pulse. 39 00:03:46,410 --> 00:03:52,560 Then we should modify the registers and send out to some segment code corresponding to the counter number. 40 00:03:54,170 --> 00:03:57,920 For this purpose, we can call to get someone segment code function. 41 00:04:02,590 --> 00:04:08,590 Open the test bench, Khaddafi, and include the design header file and the design top function prototype. 42 00:04:09,610 --> 00:04:16,180 Opened its main source file and include acquired Weatherford's then defined EMAP between seven segment 43 00:04:16,180 --> 00:04:18,970 code and the numbers between zero and nine. 44 00:04:20,780 --> 00:04:25,360 We use this map to decode the seven segment code to have more readable output on this screen. 45 00:04:26,950 --> 00:04:30,970 Then right, the main function and define the status variable and return that. 46 00:04:32,710 --> 00:04:36,760 Let's define three variables corresponding to the design function arguments. 47 00:04:38,240 --> 00:04:45,650 We can use a for loop to generate a few pulses for the design and then we use two more for loops to 48 00:04:45,650 --> 00:04:47,090 generate wider pulses. 49 00:04:51,420 --> 00:04:59,160 After writing the code, let's perform the simulation, check out what you can see, that the counterinsurgents, 50 00:04:59,310 --> 00:05:01,500 when it receives a positive pulse on its. 51 00:05:30,310 --> 00:05:36,790 Now synthesize the code and look at the analysis perspective, the design as a single cycle, sequential 52 00:05:36,790 --> 00:05:37,150 second. 53 00:06:03,310 --> 00:06:05,590 That's far from the ideal school simulation. 54 00:06:06,100 --> 00:06:10,070 Don't forget to dump all signals for inspecting their weapons. 55 00:06:14,550 --> 00:06:18,660 After finishing the simulation, click on Open Viewer IRC. 56 00:06:33,160 --> 00:06:35,290 Do we want the way we will be opened? 57 00:06:41,080 --> 00:06:43,660 Showed you the input output and signals. 58 00:06:46,830 --> 00:06:53,370 To show the signal wave form of the internal design registers, select, yes, underscore, underscore, 59 00:06:53,370 --> 00:07:01,590 counter and a scope tap on the left, then right, click on the desired register or signal in the object 60 00:07:01,590 --> 00:07:04,320 tab and select add to wave bingo. 61 00:07:06,190 --> 00:07:09,600 The desired signal should be shown in the waveform window. 62 00:07:11,050 --> 00:07:15,240 Let's at number understate registers to the waveform window. 63 00:07:27,300 --> 00:07:31,320 Please check that with each pass and input the Kountouris increment. 64 00:07:45,410 --> 00:07:49,190 Now, let's export the article IP to be U.S. in on the project. 65 00:07:58,610 --> 00:08:02,490 Create a new Virata project with the name of Counter Daneshvar. 66 00:08:03,110 --> 00:08:06,200 Don't forget to choose the basis to report as a target FPGA. 67 00:08:33,090 --> 00:08:34,410 Create a new black design. 68 00:08:48,680 --> 00:08:54,770 At the counter and the bouncer ipis to the Vivaldi repository, I'm not a piece of the design area and 69 00:08:54,770 --> 00:08:57,830 connect them together and make the external parts. 70 00:10:27,840 --> 00:10:30,230 Change the name of ports if you wish. 71 00:10:46,560 --> 00:10:52,560 Cowritten, you can't and under proper constraints, you can find a list of constraints in the resources 72 00:10:52,560 --> 00:10:54,000 folder attached to this lecture. 73 00:11:22,630 --> 00:11:25,730 Now create the ideal rapport and generate FPGA bitstream. 74 00:11:40,590 --> 00:11:44,220 Finally, program the board and examine the counter on the board. 75 00:12:21,220 --> 00:12:24,030 How can we generate a signal with a given period? 76 00:12:25,220 --> 00:12:27,290 The next lecture will cope with this question. 77 00:12:30,550 --> 00:12:36,970 These are our takeaway messages, a counter is a digital circuit that counts up or down when it receives 78 00:12:36,970 --> 00:12:38,200 a pulse on its input. 79 00:12:39,040 --> 00:12:42,970 We need the bouncer to connect the mechanical switch to the input of a counter. 80 00:12:45,790 --> 00:12:51,940 Now, the quiz question, modify the counter description such that it can count up or down.