1 00:00:01,000 --> 00:00:06,940 In logic circuit design, we should perform a task after a predefined amount of time on several occasions. 2 00:00:07,630 --> 00:00:10,720 How can we design a timer in for this purpose? 3 00:00:11,380 --> 00:00:13,390 This structure will cope with this question. 4 00:00:15,040 --> 00:00:21,430 A timer is a digital circuit that receives at least two inputs, including a number representing the 5 00:00:21,430 --> 00:00:28,060 number of clock cycles in the timing interval and the start signal, the circuit has an output which 6 00:00:28,060 --> 00:00:30,430 indicates the end of the timing interval. 7 00:00:31,180 --> 00:00:37,870 The idea behind a timer is a straightforward let's assume that the input number is N when the timer 8 00:00:37,870 --> 00:00:44,910 receives a logical value one on the start signal it counts and clock cycles and then activates the end 9 00:00:44,920 --> 00:00:49,930 signal indicating the end of the timing interval if t denotes the clock per. 10 00:00:51,300 --> 00:00:54,120 Then the timing in turmoil is and multiply to. 11 00:00:55,500 --> 00:01:03,540 For example, if it is 10 nanoseconds and is one million, then the timing interval is ten milliseconds. 12 00:01:06,360 --> 00:01:12,360 Now, let's ride the corresponding air telescope we used to find in the state machine technique to implement 13 00:01:12,360 --> 00:01:16,860 the time our state machine has two estates idle and running. 14 00:01:18,240 --> 00:01:25,020 The top function has three arguments, two inputs and one output for define two is static variables, 15 00:01:25,230 --> 00:01:28,490 which will be synthesized into registers in harder. 16 00:01:30,400 --> 00:01:38,140 The first one holds the second state and the second one says the number of lapsed cycles, then based 17 00:01:38,140 --> 00:01:42,580 on our coding style, we should define a few variables to save the registers. 18 00:01:42,580 --> 00:01:49,150 Intermediate values also a variable to keep the design output value throughout the state machine. 19 00:01:50,980 --> 00:01:55,870 Then we have to switch cases, statement to implement the transitions in the state machine. 20 00:01:56,690 --> 00:02:00,490 Finally, the variable values should be assigned to the registers. 21 00:02:01,270 --> 00:02:04,150 As mentioned earlier, the state machine has two states. 22 00:02:04,340 --> 00:02:11,110 Initially, the circuit is in the ideal state when it receives a value of one on the start signal, 23 00:02:11,470 --> 00:02:16,540 it assigns zero to the timer variable and defined the running as the next state. 24 00:02:17,690 --> 00:02:24,430 Otherwise, it stays in the idle state, in the Iranian state, the circuit increments of time or variable 25 00:02:24,980 --> 00:02:26,480 on each rising edge of the clock. 26 00:02:27,830 --> 00:02:35,000 Until the timer variable reaches the value of N minus one, then it activates the end signal and changes 27 00:02:35,000 --> 00:02:35,960 the state to idle. 28 00:02:37,520 --> 00:02:40,770 Let's synthesize and validate this code inviter such as. 29 00:02:44,190 --> 00:02:45,750 First comes the new project. 30 00:02:47,660 --> 00:02:50,270 Choose the basis report as a target of geographical. 31 00:02:57,610 --> 00:03:02,490 Please make sure that we want the IP flow target is selected in the target area. 32 00:03:06,500 --> 00:03:11,090 Now at the design and test bench fines attached to this course as a resources. 33 00:03:12,260 --> 00:03:14,550 Have a look at the design header, unsourced fox. 34 00:03:47,620 --> 00:03:55,210 Opened the source file, it contains the main function, as usual, the status Maribelle has been defined 35 00:03:55,390 --> 00:03:57,350 to keep the correctness of the test. 36 00:03:58,700 --> 00:04:02,180 Three variables are defined as the function arguments. 37 00:04:05,160 --> 00:04:12,300 The first for Loop, which has 20 iterations, calls the timer 20 times, but because the start signal 38 00:04:12,300 --> 00:04:17,880 is zero all the time, the timer doesn't do anything and it is in the idle state. 39 00:04:19,760 --> 00:04:25,520 When the value of one is assigned to the start signal and the design competition is called, then the 40 00:04:25,520 --> 00:04:29,860 value of one is assigned to start signal and the design function is called. 41 00:04:30,590 --> 00:04:35,570 In this case, the timer is simulated for one clock cycle and goes to the running state. 42 00:04:36,230 --> 00:04:42,890 Then the second for loop with 50 iterations calls the timer 50 times while the start is zero. 43 00:04:44,170 --> 00:04:49,840 Therefore, the timer is simulated for 50 clock cycles during the simulation, the timer would be in 44 00:04:49,840 --> 00:04:55,630 the running a state for 90 clock cycles and then goes to the idle state for the rest of the simulation. 45 00:04:57,890 --> 00:05:03,890 No, that as our goal is to inspect the signals and we don't have any specific computation, the code 46 00:05:03,890 --> 00:05:05,110 doesn't check it out. 47 00:05:05,270 --> 00:05:08,650 Therefore, the test sponge always claims that the design is correct. 48 00:05:10,770 --> 00:05:13,410 Let's perform the simulation and check it out. 49 00:05:20,010 --> 00:05:26,480 In the output, we have 20 clock cycles of simulation during which the timer is in the idle state, 50 00:05:26,970 --> 00:05:33,330 when they start signal is when the timer goes to the running state for 20 clock cycles and then activates 51 00:05:33,330 --> 00:05:34,080 the end signal. 52 00:05:40,640 --> 00:05:46,400 If you synthesize the code, we see that the design needs only one clock cycle to finish and iteration. 53 00:05:52,330 --> 00:05:55,120 Now let's perform the TLC simulation. 54 00:05:56,140 --> 00:06:02,380 Don't forget to select the only option for the dumb trace feature, then open the way for viewer. 55 00:06:47,890 --> 00:06:54,410 Please check that there are 20 clock cycles between the rising age of the start signal and the end signals 56 00:06:54,430 --> 00:06:55,090 rising at. 57 00:07:07,740 --> 00:07:14,790 Switch bouncing is an interesting feature of mechanical switches, it can insert several undesired pulses 58 00:07:14,790 --> 00:07:15,790 to a digital system. 59 00:07:16,530 --> 00:07:20,450 How can we bounce a mechanical switch connected to a logic circuit? 60 00:07:20,910 --> 00:07:23,010 The next lecture will address this question. 61 00:07:25,000 --> 00:07:31,570 These are outgoing messages, a digital timer can be described as a sequential circuit that counts the 62 00:07:31,570 --> 00:07:32,500 number of clocks. 63 00:07:34,220 --> 00:07:38,120 To a state of Assam in Etchells can describe a digital timer. 64 00:07:40,320 --> 00:07:45,990 Now, the quiz question, design a 10 minute timer initialised and evaluate that on the basis three 65 00:07:45,990 --> 00:07:46,210 more.