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In the previous lecture, we developed a combination lock controller in Nicholas.

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Now, the question is, how can we synthesize and develop death invite to such as this lecture will

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address this question.

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Our combination look at this description in the previous lecture had two ports, the input and the door

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open out.

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In order to test our circuit on the basis report, we are to order inputs and two other outputs to description

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the one with ENTA input determines the validation of the number on X input.

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In other words, this input tells the state machine that the input data is already invalid and can be

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sampled.

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Two groups of Output's drive a seven segment display to show a number corresponding to the index of

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the circuit state.

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This table shows the number shown on seven segment display corresponding to each state.

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These outputs are added only for debugging purposes and for understanding the circuit behavior.

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The one with lock input closes the open door, actually, it resets the state machine and puts that

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in a state as zero.

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To give new input to the design, we can connect the input to slide switches on the basis of report

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and enter input to a push-button.

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Then whenever we change the X value, we press the push button, which will give a single cycle pulse

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to the design.

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When the design finite state machine detects a single pulse on the enter input, it reads the X value

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and changes the state appropriately.

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Let's develop our design.

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Invite the specialists.

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Creating a white essentialist project with the name of combination underscore luck dashed by the socialist

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choose combination, underscore luck as a top functionary, choose the basis to report and the target

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FPGA platform.

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Download the design and test bench fines from the resources folder attached to this lecture at the fines

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to the project.

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Let's have a look at the.

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Open the design header file after including the required Heather finds an array containing the seven

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segment codes from zero to nine is defined.

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The design fine utilizes an enumeration type to define the design the states, then it's a function

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called get underscore seven underscore segment underscore code returns, the seven segment code corresponding

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to a received number.

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Then there is a design top function.

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Which receives three inputs and generates three hours.

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First, we define a static variable representing a hardware register which holds the design state.

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We also define the corresponding variable to keep track of all intermediate values for this state throughout

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the code.

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There is also a variable that holds all the intermediate values for the door open outward argument.

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Now we should define the statement.

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It contains five states.

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It starts at the S02 state whenever the signal is one, it reads the value on X and changes the state

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if it's to the input and will also be checked in other states before reading the value on X.

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Only in the last state in which the door is open, the state machine checks the lock input to lock the

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door and goes to the zero state.

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The testimony hydrofoil includes a design header fine and defines the design prototype, the test bench

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main function sets different value on X and activates to enter signals to give a proper sequence to

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the design.

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Please have a close look at the lines.

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Now let's perform the simulation.

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The output represents the state transitions after calling the top function with proper input data.

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After performing the high level sensors, the analysis perspective confirms the single cycle design

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a scheme.

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Now let's perform the RTL CECO simulation.

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Don't forget to select the all option for the down price feature.

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After finishing the RTL school simulation process opened the wavier.

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And show the design, input and output signals as well as the design Calexico.

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Now check the state transitions.

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In the last state, that is two, three, four, six, the door is open and the door is open until we

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activate the lock input signal.

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I know that you may have noticed some slight glitches on some outfits.

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First of all, these glitches are very tiny and don't impact the function behavior.

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It seems some simulation structures behind the scene calls these glitches.

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After checking the design behavior and timing, now we should export the RTL IP ready for logic synthesis.

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In the next lecture, we will instantiate our generated IP interview via the project to perform the

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largest synthesis and program, the basis to reward for playing with our design.

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This is our takeaway message, adding some design internal signals and registers to the top function

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arguments can help to better understand the design behavior.

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Now, the quiz question trying to find a reason that causes the glitches on the output waveform in the

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article, simulation output.