How can we create a given wave form as a test vector for an input of a logic circuit inviting such a..
Sometimes we need to create a specific waveform for a logic socket input to test its functionality and
timing.
For example, assuming we should generate a single cycle pulse every four hundred nanoseconds to test
the design.
To focus on generating away from signals in a test bench, let's consider a very simple logic design
that connects its input argument to its output when they enable signal is one notice that if you simply
connect the input to the output, the description is synthesized into a combination of circuit, a simple
wire, which is not desirable in this election.
I have used the register called State in the description so it will be synthesized into sequential circuit
with the clock signal.
Let's assume the design clock frequency is 100 megahertz.
As the first example, we should generate a regular single cycle pulse with the period of 80 nanoseconds,
the pulse rate is 10 nanosecond, which is one clock period.
The input signal is in a state one four one clock cycle and seven cycles in the state.
In summary, one period of the input signal takes eight clock cycles.
Let's try the test punch code to generate such input for our design under test.
After including the required header files and the function for site we define to macro's and an M which
are 10 and eight respectively, each input signal period requires eight clock cycles and we will generate
10 periods of the input signal.
The main function returns the status variable, which is zero all the time in this example, then we
should define a few variables corresponding to the design top function arguments.
In the first function called Let's pass a zero value to the design, remember that each function call
takes one clock cycle as the design is based on the single cycle design scheme to generate one period
of the input signal, we should call the design eight times in which only during the first call the
input is one if loop can implement this condition.
To repeat the signal period 10 times, if all loop can be used and compassing the aforementioned as
it's in, therefore this code fits the design under test with the required periodic signal.
After synthesizing the code and performing the art, you'll see code simulation, this diagram shows
that signal timing, which is exactly the one required.
Now, as a second example, let's generate the following signal as a design in one period of the signal
contains eight of.
Each bit lasts for 20 hours.
The data in one period is one zero zero one one one zero one again, the design clock frequency is one
hundred megahertz.
We have a test match code similar to the previous code.
We can define an area to say the data pattern in one period of the signal, then we can call the design
function and send input data using this area.
We should notice that each data elements duration is 20 nanoseconds, which means to function calls
as each function call takes one clock cycle, which is 10 nemecek.
After synthesizing the code and performing the RTL simulation, this diagram shows the signal timing,
which is exactly the one required.
This video is the last lecture in this section.
Therefore, the next lecture will give you a few exercises to practice what you have learned throughout
this section.
These are our takeaway messages that can generate given away from signals for the design designing,
considering the single cycle design approach, the number of function calls directly determines the
number of times that an input data are applied to the design during simulation.
An area that saves the input away from data can be used in a statement to be applied to the design under
test.
Now, the quiz question right at this point to apply the following to my form, to the input of the
simple design proposed in this lecture.