1 00:00:02,390 --> 00:00:09,800 Artillery simulation provides a cycle accurate simulation for a design in Etchells, however, what 2 00:00:09,800 --> 00:00:12,440 types of variables can be seen in the waveform? 3 00:00:12,440 --> 00:00:18,070 Viewers using the surreal to parallel design example explained in the previous section. 4 00:00:18,350 --> 00:00:20,330 This lecture will address this question. 5 00:00:23,450 --> 00:00:29,240 The surreal to parallel circuit receives a sequence of bits and transfers them into the equivalent parallel 6 00:00:29,240 --> 00:00:33,160 binary data, it receives one bits in each class cycle. 7 00:00:33,980 --> 00:00:35,690 Let's consider an eight bit data. 8 00:00:35,990 --> 00:00:40,190 Then on each rising age of the clock, a data, it appears, under the. 9 00:00:43,050 --> 00:00:49,500 A one second pulse on the start input indicates the start bit of the sequence after the rising edge 10 00:00:49,500 --> 00:00:53,100 of the eighth clock, the parallel data appears on the output. 11 00:00:56,260 --> 00:01:02,410 Let's find a Test match, could we start with the C main function and define this not as variable? 12 00:01:04,050 --> 00:01:10,590 Then let's define all the variables required during a Test match coat to call the design, we should 13 00:01:10,590 --> 00:01:14,700 assign proper data to the design top function input arguments. 14 00:01:15,450 --> 00:01:17,600 If there starts, very old data is zero. 15 00:01:17,790 --> 00:01:22,920 The top function is simulated for one clock cycle, but doesn't do anything useful. 16 00:01:23,850 --> 00:01:29,730 Now, to provide surreal data and start the conversion process, we should assign the value of one to 17 00:01:29,730 --> 00:01:37,200 the start signal for one clock cycle and on each clock assign one piece of data to the input, starting 18 00:01:37,200 --> 00:01:37,980 from LSP. 19 00:01:39,000 --> 00:01:41,040 We can do this process using a full. 20 00:01:42,110 --> 00:01:48,770 Then we can exit from the loop when the conversion finishes and finally check the result with the golden 21 00:01:48,770 --> 00:01:49,070 model. 22 00:01:54,860 --> 00:01:58,830 Now, let's synthesize and examine the results invited, such as idee. 23 00:02:00,200 --> 00:02:05,930 Creative writers such as this project with the name of surreal to parallel dash writers such as. 24 00:02:06,990 --> 00:02:14,460 Don't forget to choose the bases to report as a target FPGA then include the design and test range finds 25 00:02:15,120 --> 00:02:19,110 you can download the files from the resources folder attached to this lecture. 26 00:02:22,220 --> 00:02:26,990 Performed a high level syntheses and after that performed the artillery simulation. 27 00:02:27,980 --> 00:02:32,300 If you have changed the code, you will be asked to synthesize your design again. 28 00:03:05,520 --> 00:03:09,440 Don't forget to choose the all option for the dumped race feature. 29 00:03:38,420 --> 00:03:41,330 After finishing the Article six assimilation process. 30 00:03:42,240 --> 00:03:47,330 Click on the open vapor icon, the wonder wave viewer will be opened. 31 00:03:57,580 --> 00:04:01,730 So the design, input and output signals, as well as the design clock and recent. 32 00:04:05,060 --> 00:04:11,090 I think some designs, internal notes to the waveform viewer helps the debug process after syntheses. 33 00:04:13,300 --> 00:04:18,670 For this purpose, click on the air, yes, underscore in underscore serial two part of the link in 34 00:04:18,670 --> 00:04:20,320 their scope tap on the left. 35 00:04:21,800 --> 00:04:28,940 And choose your desired internal object from the least in the objects tab in the middle, you can find 36 00:04:28,940 --> 00:04:33,860 all the registers in the design that have been survived after high level syntheses here. 37 00:04:35,350 --> 00:04:41,710 For example, choose the state, underscore Regg, underscore preregister note that the name of registers 38 00:04:41,740 --> 00:04:45,610 or other nodes in the design may have been changed slightly. 39 00:04:46,270 --> 00:04:46,630 Right. 40 00:04:46,630 --> 00:04:50,460 Click on the desired object and select Atabay window. 41 00:04:51,670 --> 00:04:55,740 The state register waveform will appear in the window now. 42 00:04:55,780 --> 00:04:56,140 Right. 43 00:04:56,140 --> 00:04:59,730 Click on the counter register and add that to the waveform as well. 44 00:05:01,220 --> 00:05:06,980 To make the values in the counter more readable, you can change the right mix of values to sign the 45 00:05:06,980 --> 00:05:07,400 simple. 46 00:05:10,160 --> 00:05:13,780 You can also add other objects to the way window if you wish. 47 00:05:24,560 --> 00:05:30,740 Now we can use the very forms to follow the design behavior, as can be seen, the single cycle pulse 48 00:05:30,740 --> 00:05:36,170 on the serial start input, it starts the process and on each rising edge of the clock, the circuit 49 00:05:36,170 --> 00:05:43,340 receives an input and changes the state and council registers, and it finishes the process after receiving 50 00:05:43,340 --> 00:05:44,270 eight database. 51 00:05:48,540 --> 00:05:53,440 To test some circuits during simulation, we should apply several data to their inputs. 52 00:05:54,920 --> 00:06:02,090 These data can shape a signal why for now, the question is how can we generate a given input waveform 53 00:06:02,090 --> 00:06:05,470 in a test which the next lecture will answer this question? 54 00:06:08,300 --> 00:06:14,000 These are our takeaway messages and some of the design internal notes and registers to the waveform 55 00:06:14,000 --> 00:06:18,770 viewer provides a better debugging environment for our TLC call simulation. 56 00:06:19,520 --> 00:06:26,300 Servite registers after high level sentences are good candidates to look at their waveforms for debugging 57 00:06:26,300 --> 00:06:26,920 purposes. 58 00:06:30,610 --> 00:06:36,760 Now, the quiz question in the last waveform explained earlier in this lecture, Why have the states 59 00:06:36,760 --> 00:06:42,930 register and the counter value changed one clock cycle after changes under the input?