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How can we run to cities for the single cycle parallel to sell your circuit explained in the previous

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section?

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This letter will explain how to write this Test match.

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To show your circuit explained in the previous section, receives two inputs and generates three outputs,

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a single cycle pulse commands the circuit to start the parallel to Cirio conversion, and it takes eight

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clock cycles to send out an eight bit data.

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The proper test bench should enable us to evaluate the circuit in each clock cycle.

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As we know, each execution of the circuit based on the single cycle design approach takes one color

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cycle to finish.

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So if we call the design function in the test bench, fine, we expect one clock cycle of simulation.

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This feature of the single cycle design approach helps us to have a second accuracy simulation that

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is not available under other design techniques.

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Let's show that for the panel to Serializer.

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Anticipation starts with the sea main function.

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As usual, we define this not as viable to represent the correctness of the design.

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We should also define the variables used along the Test match code.

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Now we can assign proper values to the design input arguments and then call the design top function.

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Call runs a design once, which takes one click cycle in the single cycle design technique, known that

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only calling the design top function advances the simulation clock.

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So assigning values to variables is done in zero.

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Simulation three.

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During the first call, the design does nothing as the beginning input signal is.

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We can then assign the value of one to the biggest signal and command of design to start conversion.

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We should remember to write zero to the design signal after one design function.

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This process ensures the creation of a single cycle pulse on the beacon signal.

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Also, we can read the output signals after the design function call.

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We can repeat the function.

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Call as many clock cycles as we want.

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Here, a forum called The Design eight times, then we can check the results and modify the status variable

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appropriately.

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In the next lecture, we will develop a test bench for the serial to parallel circuit explained in the

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previous section.

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These are our takeaway messages.

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Considering the single cycle design techniques, each designed to function called in a test bench,

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takes one simulation clock, other statements in a test bench do not take any simulation clocks and

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will be done in zero time.

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Now, the question down of the parallel to serial code, which is in the resources folder attached to

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this lecture and examine the simulation as well as the artillery code simulation waveforms.