1- Describe a circuit that adds numbers between 1 and n. The circuit has one input to start and a 16-bit input to receive n. It also has five outputs.

acc_out: 16-bit results

acc_vld: 1-bit that shows the data on the is valid

overflow: 1-bit that determine an overflow during the calculation

The circuit also shows the output validation on a 7- segment display, so it has two groups of signals to drive a 7-segment.

seven_segment_data: 8-bit 7-segment code

seven_segment_enable: 4-bit 7-segment control

In the case of overflow, the 7-segment shows the letter E to represent Error. If there is no overflow and the data is valid, the 7-segment display shows the letter O. Otherwise, it is off.

The 16-bit input is connected to slide switches on the Basys3 board.

The input is connected to the UP push-button.

The 16-bit output is connected to LEDs.

As we do not have enough LEDs on the board, the acc_vld and overflow outputs are not connected to the board.

2- Describe a sequential circuit in HLS that finds the maximum number in a sequence of positive integers.

The circuit has two inputs and one output. The input data appears as a sequence on the in_data input, and when it is ready, a pulse on the enter_data input informs the circuit. Then circuit samples the data and update the maximum number and send that on the out_max output.

The circuit output should be reset by the sequential circuit rest signal that is added to the final design by the synthesis tool automatically.

3- Describe a digital circuit is HLS that find the pattern of 2, 4, 7 in an input sequence of positive integer numbers.

The circuit has two inputs and one output. The input_sequence is connected to slide switches on the Basys3 board. The enter_data input is connected to the UP push-button. Finally, the pattern_found output is connected to an LED on the board.

The 16-bit input_sequence receives numbers one by one. Whenever an input number is ready, a pulse on the enter_data informs the circuit to take an input sample. The output signal becomes “1” if the pattern is found in the input sequence. Otherwise, it is zero.

Perform the C-Simulation and Co-Simulation in the Vitis-HLS and make sure that the design is correct.

However, instantiating the design IP in Viviado does not generate the expected output. What is the reason? Later in this course, we solve the problem.