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How can we evaluate our parallel to surreal and surreal, to parallel designs and check their functionality

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and practice this lecture, we'll handle this question using what is such?

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And we want to design it.

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In order to evaluate our designs, we synthesize them separately using white Essentialists and generate

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the corresponding arc.

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Then we integrate them and Nevada project and connect them together.

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First, then you want a socialist project with the name of parallel to Sario Dash Livaditis.

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Choose parallel to serial as a design top function name to the basis three more at the Target FPGA platform.

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Make sure that if we want an IP flow target is selected as the floor targets.

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Create the design and test bench finds as viticulturist creates the fires outside the project folder

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by default, make sure to create the finds inside the project folder.

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Upon the design, Heather find and include the AP underscore that Heather.

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Then define the macro end, which is equal to it now open the design source file and include the Hanafi.

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Then the design function that accepts five arguments, two inputs and outputs.

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At the port, interfaces define a static variable called count and initialize that with that.

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Then check the input, begin, if it is one, then assign zero to count, ready to convert parallel

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data to Sario, then through a chain of, if else statements implements the functions behavior, as

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mentioned earlier in this section.

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Open the test, ban Sharafi, include the design header file and the design top function prototype.

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Could be the parallel to Sariel Dash TV that five content into the test page Sourcefire, you can find

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this file in the resources folder attached to this lecture.

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I will explain how to write a test bench file for a single cycle design flaw in a separate section.

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Let's just have a quick review over this test bench by the top function is called at line 18.

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While the design signal is zero, then the design does not do anything.

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Then the design is called eight times.

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Why are the fall line 21 notice that only through the first call.

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The begin signal is one.

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So the designer starts to convert the input parallel data into serial data and sends one data point

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out during each function called the if statement at the line twenty eight checks the design functionality.

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Now we can perform the simulation after finishing the simulation, check the outputs if it is equal

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to the input panel data.

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Now perform the synthesis.

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Have a look at the analysis perspective as it proves the single cycle article description for our analysts

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code.

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Let's look at the full synthesis report.

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Detailed design consists of 33 flipflops and 151 one lookup tables, and all ports are synthesized into

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simple wires as a design is sequential.

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The clock on reset signals are added to the final hardcore.

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Called RTL Siecle Simulation, select all option in the dumped race feature.

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After finishing the simulation, the open view icon will click on that to open the all the way from

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the.

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Sure, the design input output clock and reset signals and check their waveforms.

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Now export the corresponding yorgi.

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We should also generate the we want IP corresponding to the therriault to parallelled circuits, so

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create a new wireless such as project with the name of serial to parallel.

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That's why to such a list, choose the basis to be born as a target FPGA platform.

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Download the design and test bench files from the resources folder attached to this lecture, then add

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them to the created winter such as project.

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Investigate the design parts.

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Have a look at a test by Sourcefire to follow Bodyline 21 called the design function eight times only

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during the first call.

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The start underscores, underscore, underscore on underscore data signal is one that indicates the

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start of conversion after the eighth function call, then conversion should be one and then the output

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is valid.

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The test bench also compares the parallel data generated by design with the original data, and if they

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match, the test would be successful.

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Called the synthesis process, inspect analysis perspective and ensure that the description is a single

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cycle Ortel design.

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Now perform the artillery simulation.

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Don't forget to select the all option for dumb trace feature.

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Click on the Open Viewer IRC.

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And if you want to wave your sure, the design, input, output and clock signals, please check the

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generator parallel data at the eight o'clock cycle after the positive pulse on the surreal underscore

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start signal.

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Now, generically, we want IP by running the export archil task.

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Now, we should connect the generated IPS together and check our design on the basis rebought.

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For this purpose, created what the project with the name of parallel to Sariel to parallel Dashwood

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to the base, is to report as the underlying FPGA platform.

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Create a new black design, then add the generated IP into the Viviendo repository.

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Now, find the IPIS and add them to the design area.

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Connect IP together and make the external inputs and outputs change the external port names Ashong.

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Now we need a set of physical constraints to connect the external power to the proper FPGA pins, you

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can find the constraint fight in the resources folder attached to this lecture.

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Right, click on the concentrate folder and select add resources then in the ad resources page ensured

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that the ad or create constraints is selected.

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Then click on Create File Bottom and choose the parallel to Sariel to parallel as the filing.

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Open them to concern fines and face the constant fire content that you just download.

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Have a look at the news constraints.

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Now, right, click on the design and create the article wrapper, then run the generator out to products

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task.

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Following that, click on the generate bitstream link.

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After generating the FBI bitstream program, the board and examine the design.

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The design reads eight slide switches in power and converts them to serial data and it turns them back

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to power and shows them on eight eles.

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To start this task, you should press the push button whenever you change the switch is a status.

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This video was the last lecture explaining the design ideas in this section.

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So the next lecture will give you some exercises to master what you have learned by now.

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These are our takeaway messages, a complex sequential design can be represented by a data photograph

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in which each note can be an IP generated by the toolset.

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They've evolved ideas can easily build the dataflow of an intricate design by connecting IPIS together.

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Now, the police question connect to 16 bit parallel to surreal and surreal, two parallel ipis in Rebadow

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and generate FPGA bitstream.