1
00:00:01,080 --> 00:00:04,760
In this lecture, we are going to design a circle to parallel Converse.

2
00:00:05,850 --> 00:00:11,370
We will follow the same design approach used in the previous lecture based on the single cycle design

3
00:00:11,370 --> 00:00:11,880
technique.

4
00:00:13,990 --> 00:00:21,370
A surreal parallel convertor receives a stream of data sequentially and saves that in a multi bit register

5
00:00:21,760 --> 00:00:24,880
and sends the parallel data out at the end of the conversion.

6
00:00:25,030 --> 00:00:32,730
For example, if the circuit received the sequence value of one zero one zero zero one one one, the

7
00:00:32,770 --> 00:00:36,400
output would be one one one zero zero one zero one.

8
00:00:38,270 --> 00:00:43,820
We also consider an input signal called start and then output signal called end.

9
00:00:45,980 --> 00:00:50,450
Duvalier won on the start signal commands a convertors to start the conversion.

10
00:00:51,360 --> 00:00:57,080
The signal is activated when the last bit received and the parallel output is available and valid,

11
00:00:57,750 --> 00:01:00,840
this timing diagram shows the behavior of the final design.

12
00:01:01,410 --> 00:01:04,950
The pulse on the start signal indicates the arrival of the first.

13
00:01:05,910 --> 00:01:11,150
Then second counts to receive eight meets and keep them in internal register.

14
00:01:11,850 --> 00:01:18,870
When receiving the last bit, the received a data can be accessed on the design output and the end signal

15
00:01:19,020 --> 00:01:19,830
goes to one.

16
00:01:21,910 --> 00:01:29,170
Let's write this code for the serial to parallel convert, the function has four arguments to inputs

17
00:01:29,170 --> 00:01:30,190
and outputs.

18
00:01:31,320 --> 00:01:37,600
We should define three static variables that will be synthesized into registers in the generated article

19
00:01:37,620 --> 00:01:37,970
code.

20
00:01:38,700 --> 00:01:44,170
The first variable called aState Underscore Regg will hold the received data.

21
00:01:44,820 --> 00:01:52,590
The second one, named AI underscore underscore out, holds the output value and the last one will keep

22
00:01:52,590 --> 00:01:54,480
the number of receive its.

23
00:01:56,690 --> 00:02:02,590
The first two variables are initialized to zero and the last one is initialized with.

24
00:02:03,920 --> 00:02:11,210
We also define two arrivals to save the next value of the counter and the state underscoring, let's

25
00:02:11,210 --> 00:02:16,700
call them next underscore counter and underscore state respectively.

26
00:02:17,570 --> 00:02:23,420
Later in this course, I will explain the idea behind these 10 priority variables in a dedicated section.

27
00:02:25,540 --> 00:02:31,120
And if a statement checks the start, underscore serial, underscore data signal, and if it's one,

28
00:02:31,420 --> 00:02:36,480
it assigns zero to the next underscore counter valuable, ready for receiving their serial data.

29
00:02:38,000 --> 00:02:43,850
The next, his statement checks, the next underscore counter value to receive data if the next underscore

30
00:02:43,850 --> 00:02:49,070
Cantor is less than N minus one, there are data is shifted into the next underscore.

31
00:02:49,100 --> 00:02:51,530
A state variable was the end on the score.

32
00:02:51,530 --> 00:02:53,000
Conversion output is zero.

33
00:02:53,720 --> 00:02:57,140
The next underscore counter is incremented in this case.

34
00:02:58,260 --> 00:03:03,870
If the next underscore country is in minus one, then the rest of it is shifted into the next, underscore

35
00:03:03,870 --> 00:03:06,450
a state variable as a last bit.

36
00:03:07,860 --> 00:03:13,520
The next underscore Kountouris incremented and the end underscore conversion signal is asserted to one.

37
00:03:14,250 --> 00:03:21,570
In addition, the final parallel data is set to output through the underscore underscore outrageous.

38
00:03:22,710 --> 00:03:28,890
Finally, if the next underscore counter is greater than N minus one, the second does not accept any

39
00:03:28,890 --> 00:03:29,610
receipt data.

40
00:03:31,250 --> 00:03:36,860
After finishing the statement, the value of temporary variables should be assigned to the corresponding

41
00:03:36,860 --> 00:03:40,880
registers, notice that the next variable data is received.

42
00:03:41,030 --> 00:03:45,560
If a underscore Sariel underscore data signal becomes one again.

43
00:03:48,160 --> 00:03:50,800
This diagram shows the structure of our design.

44
00:03:52,260 --> 00:03:58,710
Please note that the sequential circuit generates two types of outputs to underscore convergent output

45
00:03:58,710 --> 00:04:05,460
signal is generated by the combination of circuit directory and the output is driven by a register.

46
00:04:06,750 --> 00:04:12,110
We should pay special attention to the output signals generated by the combination or circuit directly.

47
00:04:12,660 --> 00:04:14,740
Let's explain that in a separate slide.

48
00:04:17,400 --> 00:04:23,130
Doubt produced by the combination of circuit directly might be the subject of glitches, if in that

49
00:04:23,130 --> 00:04:29,400
particular application glitches are not acceptable, then the output should be derived by a register

50
00:04:29,520 --> 00:04:30,350
or a flipflop.

51
00:04:30,960 --> 00:04:35,400
Glitches are transient voltage or current spikes that corrupter signal.

52
00:04:36,030 --> 00:04:41,880
Their occurrence is illustrated in this figure, which shows a simple and gate generates output.

53
00:04:43,330 --> 00:04:45,850
When any input is low, the output must be low.

54
00:04:46,330 --> 00:04:53,650
However, depending on the propagation delays, B might arrive after A causing a glitch to occur.

55
00:04:53,860 --> 00:04:54,520
And why?

56
00:04:56,490 --> 00:05:03,060
One solution to avoid glitches is using flipflop or register to save the intermediate values and then

57
00:05:03,060 --> 00:05:04,410
drives the output signal.

58
00:05:05,300 --> 00:05:08,960
In our design, we use such a register for the aout.

59
00:05:12,260 --> 00:05:17,960
In order to evaluate our parallel to surreal and surreal parallel design and action, we should connect

60
00:05:17,960 --> 00:05:19,940
a few hardcore IP modules together.

61
00:05:20,360 --> 00:05:26,960
Actually, in a general case, designing sequential logic circuits usually requires a few hardware modules

62
00:05:27,080 --> 00:05:27,980
work together.

63
00:05:29,110 --> 00:05:35,710
How can we integrate several ipis generated by Etchells in the revised idee to design a complex system?

64
00:05:36,130 --> 00:05:38,860
Answering this question is the goal of the next lecture.

65
00:05:43,910 --> 00:05:45,590
These are our takeaway messages.

66
00:05:46,690 --> 00:05:50,830
The single cycle design approach can describe a surreal to parallel convert.

67
00:05:51,860 --> 00:05:57,950
A sequential circuit can generate two types of output, one is generated by the combination of circuit

68
00:05:57,950 --> 00:06:05,090
directly and the other is driven by a radius, the output produced by the combination of circuit darkly

69
00:06:05,390 --> 00:06:07,310
might be the subject to glitches.

70
00:06:10,890 --> 00:06:17,280
Now, the quiz question describe a sequential second initialised to convert a 16 bit surreal data to

71
00:06:17,280 --> 00:06:18,720
a 16 bit parallelled it.