1 00:00:02,510 --> 00:00:06,830 How can we use a single cycle design idea to describe a sequential search? 2 00:00:08,000 --> 00:00:11,370 Let's take a simple second example and follow the design approach. 3 00:00:14,780 --> 00:00:18,590 Our sequential second example is a parallel to Sario convert. 4 00:00:19,660 --> 00:00:25,990 There are several ways to implement a parallel to convertor, probably our implementation here is not 5 00:00:25,990 --> 00:00:32,290 the most efficient, but it is a very instructive example to show our design techniques. 6 00:00:34,910 --> 00:00:42,290 This circuit receives an eight bit of data through an eight Beatport and sends that out bit by bit in 7 00:00:42,290 --> 00:00:47,120 each cycle, it sends one bit out, starting from the least significant bit. 8 00:00:48,740 --> 00:00:55,590 We also onto other outputs to the design to indicate the first bit and the last bit in the output sequence. 9 00:00:56,390 --> 00:01:02,180 Therefore, this would be the timing diagram of the circuit execution during the first cycle. 10 00:01:02,330 --> 00:01:02,890 The start. 11 00:01:02,960 --> 00:01:10,010 It is one and that the output carries the first bit of data, which is one during the second clock cycle 12 00:01:10,490 --> 00:01:12,270 has the second bit, which is zero. 13 00:01:13,070 --> 00:01:15,710 This behavior continues to the eighth clock cycle. 14 00:01:16,820 --> 00:01:22,270 Just during the eight o'clock, the end output is one indicating the end of the conversion. 15 00:01:26,340 --> 00:01:32,580 This figure shows the same signals generated by White House officials after synthesizing our design 16 00:01:32,670 --> 00:01:35,110 and running the article Sea Coast Simulation. 17 00:01:40,820 --> 00:01:46,730 Let's consider our convert, it consists of a combination of circuit and a set of reforms to save the 18 00:01:46,730 --> 00:01:52,610 secular states, actually their states represents the number of bids sent out serially. 19 00:01:53,240 --> 00:01:56,470 In other words, it counts the number of processed meats. 20 00:01:57,350 --> 00:02:03,530 We assume that throughout the design execution, the input provides the input value and it is a SABL. 21 00:02:07,530 --> 00:02:13,830 In the single cycle design approach, we should write a function that reads the state sends one bit 22 00:02:13,830 --> 00:02:15,780 out and modifies the state. 23 00:02:18,760 --> 00:02:24,610 Before starting to code, let's add another input signal to our design, which commands the circuit 24 00:02:24,610 --> 00:02:27,590 to launch the conversion, the signal is called begin. 25 00:02:28,360 --> 00:02:32,750 We assume that the value of one on this signal lasts for one clock cycle. 26 00:02:32,980 --> 00:02:37,420 So when our circuit detects the level of one, it starts the conversion. 27 00:02:45,890 --> 00:02:51,980 Now, let's describe the circuit behavior, why a flowchart diagram, please recall that the circuit 28 00:02:51,980 --> 00:02:54,590 has a counter as its state variable. 29 00:02:55,510 --> 00:03:01,120 The designer starts with checking the logic of value on the beacon signal, if it is one, it resets 30 00:03:01,120 --> 00:03:04,660 the counter to zero and then checks the counter value. 31 00:03:05,850 --> 00:03:11,010 If the signal is zero, it directly checks the counter value without any extra work. 32 00:03:12,520 --> 00:03:16,570 Based on the value in the counter variable, there are four parts in the code. 33 00:03:17,550 --> 00:03:20,790 If the counter is zero, then the circuit should start conversion. 34 00:03:21,900 --> 00:03:28,920 Therefore, it activates the surreal underscore start signal and puts the LSP bit on the output line 35 00:03:29,280 --> 00:03:30,600 and commence the count. 36 00:03:33,130 --> 00:03:39,280 If the counter is less than N minus one, where endnotes the number of bits in the input data here and 37 00:03:39,310 --> 00:03:46,540 is eight, it sends out the next bits and increments, the count when the countdown reaches the value 38 00:03:46,540 --> 00:03:53,200 of minus one, which indicates the last bit, it activates the surreal underscore and signal, sends 39 00:03:53,200 --> 00:03:58,990 the mystery to the output and puts the end value to the counter to stop the conversion in the next iteration. 40 00:03:59,350 --> 00:04:05,080 If the counter is N, which is not any of the aforementioned conditions, then the circuit does not 41 00:04:05,080 --> 00:04:06,160 do anything useful. 42 00:04:09,250 --> 00:04:14,530 Notice that this flow chart represents the second functionality during each collect cycle. 43 00:04:14,980 --> 00:04:21,310 In other words, performing one iteration of this flow chart from the start to the end takes only one 44 00:04:21,310 --> 00:04:21,940 clock cycle. 45 00:04:25,390 --> 00:04:26,600 Let's start coding. 46 00:04:27,220 --> 00:04:32,950 We need a top function that receives two inputs and eight data and the biggest single. 47 00:04:33,900 --> 00:04:39,060 And generates three outputs, the serial output, the start and end signals. 48 00:04:41,060 --> 00:04:48,500 Then we define a static variable named count to count the number of processed bits, we should initialize 49 00:04:48,500 --> 00:04:49,520 that to an. 50 00:04:51,210 --> 00:04:56,190 Firstly, we should check the biggest signal and reset the counter if it is one. 51 00:04:57,350 --> 00:05:06,320 Then we need an if statement to distinguish for cases such as Eitel, the first bit, the last bit and 52 00:05:06,320 --> 00:05:07,080 the other bits. 53 00:05:09,650 --> 00:05:15,440 When the count is zero, the code should assign the logic value one to the start output signal and the 54 00:05:15,440 --> 00:05:17,420 logic value is zero to the end signal. 55 00:05:18,020 --> 00:05:24,600 In addition, it should send out the first data with wire the the output and then increment the count 56 00:05:24,830 --> 00:05:30,140 state variable when the count is seven, which means that the last bit is going to be processed. 57 00:05:30,950 --> 00:05:37,340 The code should set the logic value of one to the end signal and the zero logic value to the start. 58 00:05:38,030 --> 00:05:44,720 Then send out the last bit of data and reset the count state variable to n if the count variable is 59 00:05:44,720 --> 00:05:52,760 less than seven to start and end signal or zero and the corresponding data is assigned to download also 60 00:05:53,030 --> 00:05:55,130 the count, the state variable is increment. 61 00:05:57,250 --> 00:06:01,210 Finally, the Ellis case determines the of the United States. 62 00:06:04,430 --> 00:06:10,760 As the second example, the next lecture will explain unnaturalness code to describe a surreal to Parrello 63 00:06:10,760 --> 00:06:11,300 convert. 64 00:06:14,320 --> 00:06:21,130 These are our takeaway messages, a parallel to Sergio convertor sends out one bit of the parallel data 65 00:06:21,310 --> 00:06:22,750 on each page of the clock. 66 00:06:24,160 --> 00:06:28,510 A single cycle design flaw can be used to implement a parallel to Sariel convert. 67 00:06:29,760 --> 00:06:33,840 It's nothing valuable can be used as a counter to save the circuit state. 68 00:06:36,820 --> 00:06:43,260 Now, the quiz question modifying the parallel to sell your code to send out serially a 16 beat update.