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The register is a set of flipflops with the shared control signals such as clock and reset signals,

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how can we describe a scene and HLS code?

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This lab answered this question by implementing the same design example explained in the previous lecture.

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Our design example in the previous lecture consisted of three flipflops connected together as a shift

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register.

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Here we are going to describe the same design using a multiple static variable notice that usually the

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most right bit is the least significant it and is denoted by index zero.

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Consequently, the most right bit is the most significant bit and is denoted by index and minus one

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square and is the number of bits in the variable.

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First of all, let's create a new White House project with the name of DFS under a school register.

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That's such.

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Choose the basis three board and the target the platform.

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Make sure that we want IP floor target is selected under the floor target.

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A design source and interface also create a New Testament source and Weatherford's make sure to save

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the files inside the project folder.

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In the design there, fine include the AP Underscore Edge in the design Sourcefire first include the

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header file and then define the top function with two arguments defining a static variable of type API,

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underscore you into three and initialize that to zero, then shift unregister content one bit to the

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right more hour at the input data into the mouthpiece of the register.

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In the end, I signed the register to the argument, let's add the port interfaces later and see what

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would happen.

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Now, we should try to test match code, open the Test match header file and include the design header

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file and then add the design top function prototype, open the test open source file and define the

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main function, define the status variable and return that as usual.

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Then let's call the design top function several times with different input values.

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Note that as our goal in this test bench is viewing the design output waveforms.

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We have not checked the results and the test bench always claims that the design is correct.

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Now we can simulate our description.

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The output confirms that the right shift is performed in the design.

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Now, let's synthesize the code.

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Let's look at the full synthesis report.

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We can see that the hardware design uses for flipflops among which tree implements the state variable,

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and one is for control purposes generated by the synthesis to.

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As we haven't explicitly defined the port interfaces, the HLS tool has considered their default interfaces.

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I will talk about these interfaces later in discourse now let's add the design interfaces and synthesize

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the code again.

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To see the sentences waveform first, we should run our TLC code simulation, please make sure that

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you have selected all Allport in the dumps resorption.

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After finishing the article, Zikos Simulation, click on the Open Wave.

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Do we want away from viewer will appear?

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Shoddy design put an end to the arguments as well as the clock signal.

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Check that the design outputs are shifted to the right.

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As this video is the last lecture in the section that explains IDF concepts in the next lecture will

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give you a few exercises to review what you have learned throughout this section.

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This is our takeaway message.

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A multiple static variable can be used to describe a shift register in an Alesco.

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Now, the quiz question design a sequential logic circuit in Etchells that describes a four bit shift

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register that performs the left shift and accepts the new input as its LSP.