How can we describe a simple sequential circuit connecting a beautiful flopsy necklace, this lecture
copes with this question.
In this example, we are going to describe these thrifty flipflops connected together sequentially,
the second has one binary input and three binary outputs.
First of all, Ron, the White House and create a new project to create a new project, click on the
Create Project Link in the White House welcome page.
Then choose a project, name and location, for example, choose DFS.
Why does such a list as a project name then for the top function name, enter DFS.
Now you should select the Basis History Board as a target platform.
Click on the ellipsis icon in the part selection section, then find the board and select that.
Please notice that in the flow target section delivered IP full target option and select.
We should create a design file under the source folder in the project for this purpose, right?
Click on the source folder index for review and select the new file option.
Choose a name for the file, for example, DFS, DOT, CPB.
Notice that such a list create the file outside the project folder by default.
So double click on the project folder to create the fine inside the project directory.
After creating the design finds create a test by Sawsan Heather finds in the test bench folder.
And the design had a fine first include the underscore in header.
This project doesn't use this hydrofoil, but as we use this header file most of the time in this course,
it is a good practice to include that all the time.
And the design source file first include the header file, then defined the design top function with
the name of the Effervesce, which has four boolean arguments, one input and three outputs.
Then, as we should have three flipflops in our design, define three static boolean variables and initialize
them to zero to connect these different flops together, we use normal variable assignments.
Please notice the order of assignment's.
First, we assign death to to death three.
Then of one to death, too.
And finally, we are seeing the input value to the former.
Then we should assigned a static variables to the function arguments.
Now we need to assign proper interfaces to the top function arguments.
We use AP underscore, not interface for function arguments to implement them with simple wires and
AP underscore Setara underscore none to the top function to ignore any module level control signals.
Now, let's prepare the test benchmarks in the Test match, Gadaffi include the design header fine and
the design top function prototype, then in the test by Sourcefire defined the main test benchtop function.
Please recall that the main function should return zero if the design is correct and a non-zero value
of the design test goes wrong, and we as designers are responsible for checking the design functional
correctness, the status variable is defined for this purpose.
Defined three boolean variables and called the design top function five times each time we choose a
different value for the input.
The also print the function arguments on the screen for inspection.
Let's save the file and then run the simulation.
Click on the simulation icon.
If you don't have any typos in your code, then the results will appear on the screen, you can see
that by calling the top function in the test bench D.F., samples of the input value and the other type
of outputs are shifting one bit to the right.
As can be seen, it's a function call needs only one clock cycle to finish.
Now they can perform the sentences and generate the corresponding article code.
After synthesizing the design successfully, the White Essentialists shows the sentence a summary report.
If you would like to know more about the center's results, please have a look at the center's report
folder, which contains a report filed for the top level function and one for every SORP function that
has not been in line into a high level function by Wiktor, such as the report for the top level function
provides details on the entire design.
As can be seen, they design only utilizes three flipflops and nothing else.
Also, all the ports are implemented as simple wires.
As a second is sequential, there are two other signals in the generated article design clock and recent.
Now, let's perform the artillery simulation.
So the whole option under the dump trace feature and press.
After finishing the simulation, click on the viewer IRC, the world will be opened.
And you can examine the signals on the design inputs and outputs.
As can be seen on the rising edge, the binary value and the input is passed into F1 output and other
DF outputs are shifted to the right.
In the previous lectures, we learned that the multimedia static variable can be mapped to a register.
Now the question is, how can we use a multiple static variable to implement the connected D.F. example
explained in this lecture?
The next lecture will answer this question.
These are our takeaway messages.
This is of connected, the flipflops can act as a shift register that shifts the data to the right on
the rising edge off the clock.
Now the question, how to modify the project parameters to remove the reset signal from our design and
implement this Sakar.