1 00:00:01,220 --> 00:00:07,100 The clock signal plays a crucial role in the sequential circuit performance, however, what are the 2 00:00:07,100 --> 00:00:10,680 characteristics of a clock signaling each us in this lecture? 3 00:00:10,850 --> 00:00:15,200 I will explain the clock signal definition and characteristics inviter such as? 4 00:00:17,380 --> 00:00:23,530 Let's consider the flip flop, as mentioned before, it saves the input data value on the rising edge 5 00:00:23,530 --> 00:00:24,110 of the clock. 6 00:00:24,370 --> 00:00:31,270 However, there are two timing intervals before and after the rising edge during which the data should 7 00:00:31,270 --> 00:00:33,240 be stable and must not change. 8 00:00:34,200 --> 00:00:40,950 The timing window before the edge is called set up time and the one after the edge is called whole time. 9 00:00:41,870 --> 00:00:47,720 During this window slot, the flip flop sampled the data and says that into its state. 10 00:00:50,750 --> 00:00:57,230 The duration of these times depends on the underlying technology implementing the flipflops, therefore 11 00:00:57,410 --> 00:01:01,730 they are fixed and cannot be changed or controlled during the design. 12 00:01:02,590 --> 00:01:08,440 Instead, the combination of all circuit generating the flipflop input should provide the data before 13 00:01:08,440 --> 00:01:09,160 this window. 14 00:01:10,440 --> 00:01:14,170 And keep the data unchanged during the flipflop sampling period. 15 00:01:18,590 --> 00:01:24,430 Assume this simple sequential circuit, the flipflops are saving their data on the rising age of the 16 00:01:24,430 --> 00:01:30,470 clock, let's assume in data is one killer is one and zero. 17 00:01:30,970 --> 00:01:34,930 Now in data changes to zero before the rising edge of the clock. 18 00:01:35,980 --> 00:01:42,880 And the rising edge, the first flipflop saves the data and changes the cue from one to zero. 19 00:01:44,430 --> 00:01:51,180 The combination circuit receives this data and changes its output after its propagation delay, if the 20 00:01:51,180 --> 00:01:56,850 set up on hold time constraints are satisfied, then the new logic value Ondes will be saved in the 21 00:01:56,850 --> 00:01:59,730 second flipflop on the next rising edge of the clock. 22 00:02:01,240 --> 00:02:07,420 In this example, there is a margin between the combination of circuit propagation delay and the clock 23 00:02:07,430 --> 00:02:10,550 set up time, which is usually called exactly. 24 00:02:10,960 --> 00:02:12,780 This means the clock could be fast. 25 00:02:13,450 --> 00:02:20,380 However, for many reasons, such as reliability and uncertainty, designers prefer to consider some 26 00:02:20,380 --> 00:02:22,450 margins in the clock timing. 27 00:02:24,800 --> 00:02:31,610 In summary, a quiet period consists of two main parts combination logic, propagation, delay and uncertainty. 28 00:02:33,250 --> 00:02:40,060 The clock on certainty is used for high level sentences, White House HLS uses internal models to estimate 29 00:02:40,060 --> 00:02:42,570 the delay of the operations for each device. 30 00:02:43,330 --> 00:02:49,480 The clock uncertainty value provides a controllable margin to account for any increases in net delays 31 00:02:49,870 --> 00:02:53,050 due to archaeological Santos's place ungrouped. 32 00:02:57,830 --> 00:03:03,410 Now, let's have a look at the clock signal setting inviter Cegelis, the fourth system of the create 33 00:03:03,410 --> 00:03:09,440 new project Wieser invite Essentialists its solution configuration dialogue where you can define your 34 00:03:09,440 --> 00:03:10,760 design parameters. 35 00:03:11,120 --> 00:03:14,000 Two parameters are the clock period and uncertainty. 36 00:03:14,480 --> 00:03:21,260 You should specify the clock period in units of nanosecond or as a frequency value specified with the 37 00:03:21,260 --> 00:03:23,300 megahertz suffix, for example. 38 00:03:23,300 --> 00:03:24,890 One hundred and fifty megahertz. 39 00:03:26,340 --> 00:03:33,180 I specify the uncertainty as a value in nanoseconds or as a percentage of the clock per the default 40 00:03:33,180 --> 00:03:36,660 clock, uncertainty is 27 percent of the clock period in. 41 00:03:36,960 --> 00:03:37,550 Such as? 42 00:03:43,930 --> 00:03:50,350 Collect signals, save new data in the memory part of a sequential circuit and transfer the design into 43 00:03:50,350 --> 00:03:51,100 a new estate. 44 00:03:51,430 --> 00:03:54,530 But what is a sequential circuit state in the next lecture? 45 00:03:54,790 --> 00:03:57,370 I will explain the basic concepts of the states. 46 00:03:57,670 --> 00:04:03,220 More details about the states and how to use them to design a sequential circuit will be explained in 47 00:04:03,220 --> 00:04:04,020 a separate section. 48 00:04:07,690 --> 00:04:13,570 These are our takeaway messages during the setup time and whole time they put up a flip flop should 49 00:04:13,570 --> 00:04:14,080 be stable. 50 00:04:15,520 --> 00:04:21,700 They didn't collect period in Etchells has two parts combination of circuit propagation, delay and 51 00:04:21,700 --> 00:04:27,910 uncertainty, the default value of the clock uncertainty in white Essentialists is twenty seven percent 52 00:04:28,090 --> 00:04:29,080 of the clock period. 53 00:04:32,600 --> 00:04:39,280 Now, the question, if the propagation delay of a combination or circuit is seventeen point three nanoseconds 54 00:04:39,410 --> 00:04:44,700 and if you assume the default uncertainty in the White House is what would be the minimum design clock 55 00:04:44,720 --> 00:04:45,070 period?